MC908LJ12CFUE Freescale Semiconductor, MC908LJ12CFUE Datasheet - Page 217

• Manufacturer Part Number: MC908LJ12CFUE
• Description: IC MCU 12K FLASH 4/8MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ12CFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

MC68HC908LJ12
Freescale Semiconductor
—
Rev. 2.1
CHRIE — Chronograph Interrupt Enable
DAYIE — Day Interrupt Enable
HRIE — Hour Interrupt Enable
MINIE — Minute Interrupt Enable
SECIE — Second Interrupt Enable
TB1IE — Timebase 1 Interrupt Enable
TB2IE — Timebase 2 Interrupt Enable
This read/write bit enables the chronograph flag, CHRF, to generate
CPU interrupt requests. Reset clears the CHRIE bit.
This read/write bit enables the day flag, DAYF, to generate CPU
interrupt requests. Reset clears the DAYIE bit.
This read/write bit enables the hour flag, HRF, to generate CPU
interrupt requests. Reset clears the HRIE bit.
This read/write bit enables the minute flag, MINF, to generate CPU
interrupt requests. Reset clears the MINIE bit.
This read/write bit enables the second flag, SECF, to generate CPU
interrupt requests. Reset clears the SECIE bit.
This read/write bit enables the timebase1 flag, TB1F, to generate
CPU interrupt requests. Reset clears the TB1IE bit.
This read/write bit enables the timebase2 flag, TB2F, to generate
CPU interrupt requests. Reset clears the TB2IE bit.
1 = CHRF enabled to generate CPU interrupt
0 = CHRF not enabled to generate CPU interrupt
1 = DAYF enabled to generate CPU interrupt
0 = DAYF not enabled to generate CPU interrupt
1 = HRF enabled to generate CPU interrupt
0 = HRF not enabled to generate CPU interrupt
1 = MINF enabled to generate CPU interrupt
0 = MINF not enabled to generate CPU interrupt
1 = SECF enabled to generate CPU interrupt
0 = SECF not enabled to generate CPU interrupt
1 = TB1F enabled to generate CPU interrupt
0 = TB1F not enabled to generate CPU interrupt
1 = TB2F enabled to generate CPU interrupt
0 = TB2F not enabled to generate CPU interrupt
Real Time Clock (RTC)
Real Time Clock (RTC)
Technical Data
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