MC908LJ12CFUE Freescale Semiconductor, MC908LJ12CFUE Datasheet - Page 221

• Manufacturer Part Number: MC908LJ12CFUE
• Description: IC MCU 12K FLASH 4/8MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ12CFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

MC68HC908LJ12
Freescale Semiconductor
—
Rev. 2.1
MINF — Minute Flag
SECF — Second Flag
TB1F — Timebase 1 Flag
TB2F — Timebase 2 Flag
This clearable, read-only bit is set on every increment of the minute
counter. When the MINIE bit in RTCCR1 is set, MINF generates a
CPU interrupt request. In normal operation, clear the MINF bit by
reading RTCSR with MINF set and then reading the minute register
(MINR). Reset clears MINF.
This clearable, read-only bit is set on every increment of the second
counter. When the SECIE bit in RTCCR1 is set, SECF generates a
CPU interrupt request. In normal operation, clear the SECF bit by
reading RTCSR with SECF set and then reading the second register
(SECR). Reset clears SECF.
This clearable, read-only bit is set on every tick of the timebase 1
counter (every 0.5 seconds). When the TB1IE bit in RTCCR1 is set,
TB1F generates a CPU interrupt request. In normal operation, clear
the TB1F bit by reading RTCSR with TB1F set and then reading the
chronograph register (CHRR). Reset clears TB1F.
This clearable, read-only bit is set on every tick of the timebase 2
counter (every 0.25 seconds). When the TB2IE bit in RTCCR1 is set,
TB2F generates a CPU interrupt request. In normal operation, clear
the TB2F bit by reading RTCSR with TB2F set and then reading the
chronograph register (CHRR). Reset clears TB2F.
1 = Minute counter incremented
0 = No minute counter incremented
1 = Second counter incremented
0 = No second counter incremented
1 = A timebase 1 tick (0.5s) has occurred
0 = No timebase 1 tick has occurred
1 = A timebase 2 tick (0.25s) has occurred
0 = No timebase 2 tick has occurred
Real Time Clock (RTC)
Real Time Clock (RTC)
Technical Data
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