MC908LJ12CFUE Freescale Semiconductor, MC908LJ12CFUE Datasheet - Page 55

• Manufacturer Part Number: MC908LJ12CFUE
• Description: IC MCU 12K FLASH 4/8MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ12CFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

MC68HC908LJ12
Freescale Semiconductor
Note: Writing a logic 0 clears SBSW.
Addr.
$005C
$005D
$FE00
$FE01
$005A
$005B
$005E
$005F
$0059
SIM Break Status Register
SIM Reset Status Register
LCD Data Register 10
LCD Data Register 11
LCD Data Register 12
LCD Data Register 13
LCD Data Register 14
Register Name
LCD Data Register 8
LCD Data Register 9
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 10 of 12)
—
Rev. 2.1
(LDAT10)
(LDAT11)
(LDAT12)
(LDAT13)
(LDAT14)
(LDAT8)
(LDAT9)
(SRSR)
(SBSR)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
POR:
X = Indeterminate
F15B3
F17B3
F19B3
F21B3
F23B3
F25B3
Bit 7
POR
U
U
U
U
U
U
U
R
1
F15B2
F17B2
F19B2
F21B2
F23B2
F25B2
PIN
U
U
U
U
U
U
U
R
6
0
Memory Map
F15B1
F17B1
F19B1
F21B1
F23B1
F25B1
COP
U
U
U
U
U
U
U
R
5
0
= Unimplemented
F15B0
F17B0
F19B0
F21B0
F23B0
F25B0
ILOP
U
U
U
U
U
U
U
R
4
0
F14B3
F16B3
F18B3
F20B3
F22B3
F24B3
F26B3
ILAD
U
U
U
U
U
U
U
R
3
0
F14B2
F16B2
F18B2
F20B2
F22B2
F24B2
F26B2
U
U
U
U
U
U
U
R
R
2
0
0
= Reserved
F14B1
F16B1
F18B1
F20B1
F22B1
F24B1
F26B1
SBSW
Note
LVI
U
U
U
U
U
U
U
1
0
0
Technical Data
Memory Map
F14B0
F16B0
F18B0
F20B0
F22B0
F24B0
F26B0
Bit 0
U
U
U
U
U
U
U
R
0
0
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