MC908LJ12CFUE Freescale Semiconductor, MC908LJ12CFUE Datasheet - Page 191

• Manufacturer Part Number: MC908LJ12CFUE
• Description: IC MCU 12K FLASH 4/8MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ12CFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

11.5.1 TIM Counter Prescaler
11.5.2 Input Capture
MC68HC908LJ12
Freescale Semiconductor
Addr.
$0032
$0033
$0034
$0035
Timer 2 Channel 1 Status
Register Name
and Control Register
Timer 2 Channel 0
Timer 2 Channel 1
Timer 2 Channel 1
Register High
Register Low
Register Low
—
(T2CH1H)
Rev. 2.1
(T2CH0L)
(T2CH1L)
(T2SC1)
Figure 11-2. TIM I/O Register Summary (Sheet 3 of 3)
The TIM clock source can be one of the seven prescaler outputs. The
prescaler generates seven clock rates from the internal bus clock. The
prescaler select bits, PS[2:0], in the TIM status and control register
select the TIM clock source.
With the input capture function, the TIM can capture the time at which an
external event occurs. When an active edge occurs on the pin of an input
capture channel, the TIM latches the contents of the TIM counter into the
TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is
programmable. Input captures can generate TIM CPU interrupt
requests.
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
CH1F
Bit 15
Bit 7
Bit 7
Bit 7
0
0
Timer Interface Module (TIM)
= Unimplemented
CH1IE
14
6
6
0
6
13
5
5
0
0
5
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
MS1A
12
4
4
0
4
ELS1B
11
3
3
0
3
Timer Interface Module (TIM)
ELS1A
10
2
2
0
2
TOV1
1
1
0
9
1
Technical Data
CH1MAX
Bit 0
Bit 0
Bit 8
Bit 0
0
191