MC908LJ12CFUE Freescale Semiconductor, MC908LJ12CFUE Datasheet - Page 397

• Manufacturer Part Number: MC908LJ12CFUE
• Description: IC MCU 12K FLASH 4/8MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ12CFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

23.8 5.0V Control Timing
23.9 3.3V Control Timing
MC68HC908LJ12
Freescale Semiconductor
Notes:
Notes:
Notes:
Internal operating frequency
RST input pulse width low
Internal operating frequency
RST input pulse width low
1. V
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) I
4. Wait I
5. The 8kHz clock is from a 32kHz clock input at OSC1, for the driving the RTC.
6. LCD driver configured for high current mode.
7. Maximum is highest voltage that POR is guaranteed.
8. If minimum V
9. R
1. V
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
1. V
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
100 pF on all outputs. C
all outputs. C
V
information.
information.
DD
SS
SS
DD
PU1
= 0 Vdc; timing shown with respect to 20% V
= 0 Vdc; timing shown with respect to 20% V
= 3.0 to 3.6 Vdc, V
is reached.
and R
DD
measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on
PU2
DD
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait I
are measured at V
is not reached before the internal POR reset is released,
—
DD
Rev. 2.1
measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than
Characteristic
Characteristic
SS
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run I
(3)
(3)
= 0 Vdc, T
(2)
(2)
DD
A
Table 23-6. 5.0V Control Timing
Table 23-7. 3.3V Control Timing
= 3.3V.
= T
(1)
(1)
L
to T
Electrical Specifications
H
, unless otherwise noted.
DD
DD
and 70% V
and 70% V
DD
DD
, unless otherwise noted.
, unless otherwise noted.
Symbol
Symbol
RST
t
t
f
f
IRL
IRL
OP
OP
must be driven low externally until minimum
Min
Min
750
1.5
—
—
Electrical Specifications
Max
Max
—
—
8
4
DD
Technical Data
.
MHz
MHz
Unit
Unit
DD
ns
µs
.
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