MC68HC908MR16CFU Freescale Semiconductor, MC68HC908MR16CFU Datasheet - Page 101

• Manufacturer Part Number: MC68HC908MR16CFU
• Description: IC MCU 8MHZ 16K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908MR16CFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 44
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Chapter 10
Input/Output (I/O) Ports (PORTS)
10.1 Introduction
Thirty-seven bidirectional input-output (I/O) pins and seven input pins form six parallel ports. All I/O pins
are programmable as inputs or outputs.
When using the 56-pin package version:
Freescale Semiconductor
$0000
$0001
$0002
$0003
$0004
Addr.
•
•
•
Set the data direction register bits in DDRC such that bit 1 is written to a logic 1 (along with any
other output bits on port C).
Set the data direction register bits in DDRE such that bits 0, 1, and 2 are written to a logic 1 (along
with any other output bits on port E).
Set the data direction register bits in DDRF such that bits 0, 1, 2, and 3 are written to a logic 1 (along
with any other output bits on port F).
Data Direction Register A
Port C Data Register
Port D Data Register
Port A Data Register
Port B Data Register
Connect any unused I/O pins to an appropriate logic level, either V
V
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
SS
Register Name
See page 103.
See page 104.
See page 106.
See page 107.
See page 103.
. Although PWM6–PWM1 do not require termination for proper
(DDRA)
(PTA)
(PTB)
(PTC)
(PTD)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Figure 10-1. I/O Port Register Summary
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
DDRA7
PTA7
PTB7
Bit 7
R
R
R
0
0
0
= Reserved
DDRA6
PTA6
PTB6
PTC6
PTD6
R
6
0
NOTE
DDRA5
PTA5
PTB5
PTC5
PTD5
R
5
0
DDRA4
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
PTC4
PTD4
PTA4
PTB4
R
4
0
= Unimplemented
DDRA3
PTA3
PTB3
PTC3
PTD3
R
3
0
DDRA2
PTA2
PTB2
PTC2
PTD2
DD
R
2
0
or
DDRA1
PTC1
PTD1
PTA1
PTB1
R
1
0
DDRA0
PTA0
PTB0
PTC0
PTD0
Bit 0
R
0
101