MC68HC908MR16CFU Freescale Semiconductor, MC68HC908MR16CFU Datasheet - Page 198

• Manufacturer Part Number: MC68HC908MR16CFU
• Description: IC MCU 8MHZ 16K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908MR16CFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 44
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Serial Peripheral Interface Module (SPI)
15.4.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR, is set.
Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI
module by writing to the SPI data register. If the shift register is empty, the byte immediately transfers to
the shift register, setting the SPI transmitter empty bit, SPTE. The byte begins shifting out on the MOSI
pin under the control of the serial clock. See
The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register.
See
master also controls the shift register of the slave peripheral.
As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master’s
MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same time that
SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation,
198
$0044
$0045
$0046
Addr.
15.12.2 SPI Status and Control
Register Name
Configure the SPI modules as master or slave before enabling them.
Enable the master SPI before enabling the slave SPI. Disable the slave SPI
before disabling the master SPI. See
SPI Status and Control
SPI Control Register
Register (SPSCR)
SPI Data Register
SHIFT REGISTER
See page 211.
See page 212.
See page 214.
GENERATOR
MASTER MCU
BAUD RATE
Figure 15-4. Full-Duplex Master-Slave Connections
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
(SPCR)
(SPDR)
Figure 15-3. SPI I/O Register Summary
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Register. Through the SPSCK pin, the baud-rate generator of the
SPRIE
MISO
MOSI
SPSCK
SS
SPRF
Bit 7
R7
T7
R
R
0
0
Figure
= Reserved
ERRIE
NOTE
R6
T6
R
6
0
0
15-4.
V
15.12.1 SPI Control
DD
SPMSTR
OVRF
R5
T5
R
5
1
0
SPSCK
MISO
MOSI
SS
Unaffected by reset
MODF
CPOL
R4
T4
R
4
0
0
SHIFT REGISTER
SLAVE MCU
Register.
CPHA
SPTE
R3
T3
R
3
1
1
MODFEN
SPWOM
R2
T2
Freescale Semiconductor
2
0
0
SPR1
SPE
R1
T1
1
0
0
SPTIE
SPR0
Bit 0
R0
T0
0
0