MC68HC908MR16CFU Freescale Semiconductor, MC68HC908MR16CFU Datasheet - Page 190

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MC68HC908MR16CFU

Manufacturer Part Number
MC68HC908MR16CFU
Description
IC MCU 8MHZ 16K FLASH 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908MR16CFU

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
44
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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System Integration Module (SIM)
14.5.1.2 Software Interrupt (SWI) Instruction
The software interrupt (SWI) instruction is a non-maskable instruction that causes an interrupt regardless
of the state of the interrupt mask
(I bit) in the condition code register.
14.5.2 Reset
All reset sources always have equal and highest priority and cannot be arbitrated.
14.6 Low-Power Mode
Executing the WAIT instruction puts the MCU in a low power-consumption mode for standby situations.
The SIM holds the CPU in a non-clocked state. WAIT clears the interrupt mask (I) in the condition code
register, allowing interrupts to occur.
14.6.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run.
the timing for wait mode entry.
A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled.
Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred.
Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
Wait mode can also be exited by a reset. If the COP disable bit, COPD, in the configuration register is
logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode.
Figure 14-12
190
and
EXITSTOPWAIT
Note: EXITSTOPWAIT = RST pin OR CPU interrupt
Figure 14-13
R/W
Note: Previous data can be operand data or the WAIT opcode, depending on the
IAB
IDB
IDB
IAB
last instruction.
WAIT ADDR
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
$A6
Figure 14-12. Wait Recovery from Interrupt
show the timing for wait recovery.
Figure 14-11. Wait Mode Entry Timing
PREVIOUS DATA
$6E0B
$A6
WAIT ADDR + 1
$A6
$6E0C
NEXT OPCODE
$01
$00FF
$0B
SAME
$00FE
$6E
SAME
$00FD
SAME
$00FC
SAME
Freescale Semiconductor
Figure 14-11
shows

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