MC68HC908MR16CFU Freescale Semiconductor, MC68HC908MR16CFU Datasheet - Page 104

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MC68HC908MR16CFU

Manufacturer Part Number
MC68HC908MR16CFU
Description
IC MCU 8MHZ 16K FLASH 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908MR16CFU

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
44
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Quantity
Price
Part Number:
MC68HC908MR16CFU
Manufacturer:
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Quantity:
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Part Number:
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Manufacturer:
ALTERA
Quantity:
101
Input/Output (I/O) Ports (PORTS)
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a
logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
10.3 Port B
Port B is an 8-bit, general-purpose, bidirectional I/O port that shares its pins with the analog-to-digital
convertor (ADC) module.
10.3.1 Port B Data Register
The port B data register (PTB) contains a data latch for each of the eight port B pins.
PTB[7:0] — Port B Data Bits
104
These read/write bits are software-programmable. Data direction of each port B pin is under the control
of the corresponding bit in data direction register B. Reset has no effect on port B data.
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect input.
DDRA Bit
Address:
0
1
Reset:
Read:
Write:
READ DDRA ($0004)
WRITE DDRA ($0004)
WRITE PTA ($0000)
READ PTA ($0000)
$0001
PTB7
Bit 7
PTA Bit
X
X
(1)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Figure 10-5. Port B Data Register (PTB)
PTB6
6
I/O Pin Mode
Table 10-1. Port A Pin Functions
Input, Hi-Z
RESET
Figure 10-4. Port A I/O Circuit
Output
PTB5
5
(2)
Table 10-1
Unaffected by reset
PTB4
DDRAx
PTAx
4
Accesses to DDRA
Read/Write
DDRA[7:0]
DDRA[7:0]
summarizes the operation of the port A pins.
PTB3
3
PTB2
2
PTA[7:0]
Read
PTB1
Pin
Accesses to PTA
1
Freescale Semiconductor
PTB0
Bit 0
PTA[7:0]
PTA[7:0]
PTAx
Write
(3)

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