MC68HC908MR16CFU Freescale Semiconductor, MC68HC908MR16CFU Datasheet - Page 238

• Manufacturer Part Number: MC68HC908MR16CFU
• Description: IC MCU 8MHZ 16K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908MR16CFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 44
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Timer Interface B (TIMB)
17.3.1 TIMB Counter Prescaler
The TIMB clock source can be one of the seven prescaler outputs or the TIMB clock pin,
The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0],
in the TIMB status and control register select the TIMB clock source.
17.3.2 Input Capture
An input capture function has three basic parts:
Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value of the
free-running counter after the corresponding input capture edge detector senses a defined transition. The
polarity of the active edge is programmable. The level transition which triggers the counter transfer is
defined by the corresponding input edge bits (ELSxB and ELSxA in TBSC0–TBSC1 control registers with
x referring to the active channel number). When an active edge occurs on the pin of an input capture
channel, the TIMB latches the contents of the TIMB counter into the TIMB channel registers,
TCHxH–TCHxL. Input captures can generate TIMB CPU interrupt requests. Software can determine that
an input capture event has occurred by enabling input capture interrupts or by polling the status flag bit.
The free-running counter contents are transferred to the TIMB channel status and control register
(TBCHxH–TBCHxL, see
238
$005A
$005B
$0056
$0057
$0058
$0059
Addr.
1. Edge select logic
2. Input capture latch
3. 16-bit counter
TIMB Channel 0 Status/Control
TIMB Channel 1 Status/Control
TIMB Channel 0 Register High
TIMB Channel 1 Register High
TIMB Channel 0 Register Low
TIMB Channel 1 Register Low
Register Name
(TBSC0)
(TBSC1)
See page 247.
See page 250.
See page 250.
See page 247.
See page 250.
See page 250.
(TBCH0H)
(TBCH1H)
(TBCH0L)
(TBCH1L)
Figure 17-3. TIMB I/O Register Summary (Continued)
Register
Register
17.7.5 TIMB Channel
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
CH0F
CH1F
Bit 15
Bit 15
Bit 7
Bit 7
Bit 7
R
0
0
0
0
= Reserved
CH0IE
CH1IE
Bit 14
Bit 14
Bit 6
Bit 6
Registers) on each proper signal transition regardless of
6
0
0
MS0B
Bit 13
Bit 13
Bit 5
Bit 5
R
5
0
0
0
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
MS0A
MS1A
Bit 12
Bit 12
Bit 4
Bit 4
4
0
0
ELS0B
ELS1B
Bit 11
Bit 11
Bit 3
Bit 3
3
0
0
ELS0A
ELS1A
Bit 10
Bit 10
Bit 2
Bit 2
Freescale Semiconductor
2
0
0
PTE0/TCLKB
TOV0
TOV1
Bit 9
Bit 1
Bit 9
Bit 1
1
0
0
CH0MAX
CH1MAX
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
0
0
.