MC68HC908MR16CFU Freescale Semiconductor, MC68HC908MR16CFU Datasheet - Page 255

• Manufacturer Part Number: MC68HC908MR16CFU
• Description: IC MCU 8MHZ 16K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908MR16CFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 44
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

18.2.3.3 Break Status Register
The break status register (SBSR) contains a flag to indicate that a break caused an exit from wait mode.
The flag is useful in applications requiring a return to wait mode after exiting from a break interrupt.
BW — Break Wait Bit
18.2.3.4 Break Flag Control Register
The break flag control register (SBFCR) contains a bit that enables software to clear status bits while the
MCU is in a break state.
BCFE — Break Clear Flag Enable Bit
18.3 Monitor ROM (MON)
The monitor ROM (MON) allows complete testing of the microcontroller unit (MCU) through a single-wire
interface with a host computer. Monitor mode entry can be achieved without the use of V
vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit
programming.
Freescale Semiconductor
This read/write bit is set when a break interrupt causes an exit from wait mode. Clear BW by writing a
logic 0 to it. Reset clears BW.
BW can be read within the break interrupt routine. The user can modify the return address on the stack
by subtracting 1 from it.
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Break interrupt during wait mode
0 = No break interrupt during wait mode
1 = Status bits clearable during break
0 = Status bits not clearable during break
Address:
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
$FE00
$FE03
Figure 18-7. SIM Break Flag Control Register (SBFCR)
BCFE
Bit 7
Bit 7
R
R
0
Figure 18-6. SIM Break Status Register (SBSR)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
= Reserved
R
R
6
6
R
R
5
5
R
R
4
4
R
R
3
3
R
R
2
2
BW
R
1
0
1
Bit 0
Bit 0
Monitor ROM (MON)
R
R
TST
as long as
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