MC68HC908MR16CFU Freescale Semiconductor, MC68HC908MR16CFU Datasheet - Page 219

• Manufacturer Part Number: MC68HC908MR16CFU
• Description: IC MCU 8MHZ 16K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908MR16CFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 44
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

16.3 Functional Description
Figure 16-2
can operate as a free-running counter or a modulo up-counter. The TIMA counter provides the timing
reference for the input capture and output compare functions. The TIMA counter modulo registers,
TAMODH–TAMODL, control the modulo value of the TIMA counter. Software can read the TIMA counter
value at any time without affecting the counting sequence.
The four TIMA channels are programmable independently as input capture or output compare channels.
16.3.1 TIMA Counter Prescaler
The TIMA clock source can be one of the seven prescaler outputs or the TIMA clock pin, PTE3/TCLKA.
The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0],
in the TIMA status and control register select the TIMA clock source.
16.3.2 Input Capture
An input capture function has three basic parts:
Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value of the
free-running counter after the corresponding input capture edge detector senses a defined transition. The
polarity of the active edge is programmable. The level transition which triggers the counter transfer is
defined by the corresponding input edge bits (ELSxB and ELSxA in TASC0–TASC3 control registers with
Freescale Semiconductor
$001A
$001B
$001C
$001D
$001E
Addr.
1. Edge select logic
2. Input capture latch
3. 16-bit counter
TIMA Channel 3 Status/Control
TIMA Channel 2 Register High
TIMA Channel 3 Register High
TIMA Channel 2 Register Low
TIMA Channel 3 Register Low
shows the TIMA structure. The central component of the TIMA is the 16-bit TIMA counter that
Register Name
Register (TASC3)
See page 232.
See page 232.
See page 229.
See page 232.
See page 232.
(TACH2H)
(TACH3H)
(TACH2L)
(TACH3L)
Figure 16-3. TIM I/O Register Summary (Continued)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
CH3F
Bit 15
Bit 15
Bit 7
Bit 7
Bit 7
R
0
0
= Reserved
CH3IE
14
14
6
6
0
6
13
13
R
5
5
0
0
5
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
MS3A
12
12
4
4
0
4
ELS3B
11
11
3
3
0
3
ELS3A
10
10
2
2
0
2
Functional Description
TOV3
1
9
1
0
9
1
CH3MAX
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
0
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