MC68HC908MR16CFU Freescale Semiconductor, MC68HC908MR16CFU Datasheet - Page 38

• Manufacturer Part Number: MC68HC908MR16CFU
• Description: IC MCU 8MHZ 16K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908MR16CFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 44
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Memory
During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack
pointer decrements during pushes and increments during pulls.
2.8 FLASH Memory (FLASH)
The FLASH memory is an array of 32,256 bytes with an additional 46 bytes of user vectors and one byte
of block protection.
Program and erase operations are facilitated through control bits in a memory mapped register. Details
for these operations appear later in this section.
Memory in the FLASH array is organized into two rows per page. The page size is 128 bytes per page.
The minimum erase page size is 128 bytes. Programming is performed on a row basis, 64 bytes at a time.
The address ranges for the user memory and vectors are:
Programming tools are available from Freescale. Contact a local Freescale representative for more
information.
2.8.1 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase operations.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
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unauthorized users.
•
•
•
•
$8000–$FDFF, user memory
$FF7E, block protect register (FLBPR)
$FE08, FLASH control register (FLCR)
$FFD2–$FFFF, reserved for user-defined interrupt and reset vectors
Address:
Be careful when using nested subroutines. The CPU may overwrite data in
the RAM during a subroutine or during the interrupt stacking operation.
An erased bit reads as a 1 and a programmed bit reads as a 0.
A security feature prevents viewing of the FLASH contents.
Reset:
Read:
Write:
$FE08
Bit 7
0
0
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Figure 2-3. FLASH Control Register (FLCR)
= Unimplemented
6
0
0
5
0
0
NOTE
NOTE
NOTE
4
0
0
HVEN
3
0
MASS
2
0
(1)
ERASE
1
0
Freescale Semiconductor
PGM
Bit 0
0