MC68HC908MR16CFU Freescale Semiconductor, MC68HC908MR16CFU Datasheet - Page 153

• Manufacturer Part Number: MC68HC908MR16CFU
• Description: IC MCU 8MHZ 16K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908MR16CFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 44
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

FFLAG1 — Fault Event Flag 1
12.9.10 Fault Acknowledge Register
The fault acknowledge register (FTACK) is used to acknowledge and clear the FFLAGs. In addition, it is
used to monitor the current sensing bits to test proper operation.
FTACK4 — Fault Acknowledge 4 Bit
FTACK3 — Fault Acknowledge 3 Bit
FTACK2 — Fault Acknowledge 2 Bit
FTACK1 — Fault Acknowledge 1 Bit
DT6 — Dead-Time 6 Bit
DT5 — Dead-Time 5 Bit
DT4 — Dead-Time 4 Bit
DT3 — Dead-Time 3 Bit
Freescale Semiconductor
The FFLAG1 event bit is set within two CPU cycles after a rising edge on fault pin 1. To clear the
FFLAG1 bit, the user must write a 1 to the FTACK1 bit in the fault acknowledge register.
The FTACK4 bit is used to acknowledge and clear FFLAG4. This bit will always read 0. Writing a 1 to
this bit will clear FFLAG4. Writing a 0 will have no effect.
The FTACK3 bit is used to acknowledge and clear FFLAG3. This bit will always read 0. Writing a 1 to
this bit will clear FFLAG3. Writing a 0 will have no effect.
The FTACK2 bit is used to acknowledge and clear FFLAG2. This bit will always read 0. Writing a 1 to
this bit will clear FFLAG2. Writing a 0 will have no effect.
The FTACK1 bit is used to acknowledge and clear FFLAG1. This bit will always read 0. Writing a 1 to
this bit will clear FFLAG1. Writing a 0 will have no effect.
Current sensing pin IS3 is monitored immediately before dead-time ends due to the assertion of
PWM6.
Current sensing pin IS3 is monitored immediately before dead-time ends due to the assertion of
PWM5.
Current sensing pin IS2 is monitored immediately before dead-time ends due to the assertion of
PWM4.
Current sensing pin IS2 is monitored immediately before dead-time ends due to the assertion of
PWM3.
1 = A fault has occurred on fault pin 1.
0 = No new fault on fault pin 1.
Address: $0024
Reset:
Read:
Write:
Bit 7
Figure 12-45. Fault Acknowledge Register (FTACK)
0
0
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
= Unimplemented
FTACK4
6
0
0
DT6
5
0
FTACK3
DT5
4
0
DT4
3
0
FTACK2
DT3
2
0
DT2
1
0
FTACK1
Bit 0
DT1
Control Logic Block
0
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