MC68HC908MR16CFU Freescale Semiconductor, MC68HC908MR16CFU Datasheet - Page 60

• Manufacturer Part Number: MC68HC908MR16CFU
• Description: IC MCU 8MHZ 16K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908MR16CFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 44
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Clock Generator Module (CGM)
The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final
reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final
reference frequency, f
this comparison.
4.3.2.2 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two operating modes:
4.3.2.3 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter manually or automatically.
In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between
acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. See
Bandwidth Control
request and then check the LOCK bit. If interrupts are disabled, software can poll the LOCK bit
continuously (during PLL startup, usually) or at periodic intervals. In either case, when the LOCK bit is set,
the VCO clock is safe to use as the source for the base clock. See
the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a
severe noise hit and the software must take appropriate action, depending on the application. See
Interrupts
These conditions apply when the PLL is in automatic bandwidth control mode:
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1. Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the
2. Tracking mode — In tracking mode, the filter makes only small corrections to the frequency of the
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VCO. This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in
the PLL bandwidth control register. See
VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL
enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected
as the base clock source. See
tracking mode when not in acquisition mode or when the ACQ bit is set.
The ACQ bit (see
filter. For more information, see
The ACQ bit is set when the VCO frequency is within a certain tolerance, ∆
the VCO frequency is out of a certain tolerance, ∆
Acquisition/Lock Time
The LOCK bit is a read-only indicator of the locked state of the PLL.
The LOCK bit is set when the VCO frequency is within a certain tolerance, ∆
when the VCO frequency is out of a certain tolerance, ∆
Acquisition/Lock Time
CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock condition changes, toggling
the LOCK bit. For more information, see
for information and precautions on using interrupts.
Register. If PLL interrupts are enabled, the software can wait for a PLL interrupt
RDV
4.5.2 PLL Bandwidth Control
. The circuit determines the mode of the PLL and the lock condition based on
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Specifications.
Specifications.
4.3.3 Base Clock Selector
4.3.2.2 Acquisition and Tracking
4.5.2 PLL Bandwidth Control
4.5.1 PLL Control
Register) is a read-only indicator of the mode of the
UNT
. For more information, see
UNL
Circuit. The PLL is automatically in
Register.
. For more information, see
4.3.3 Base Clock Selector
Modes.
Register.
TRK
, and is cleared when
Lock
Freescale Semiconductor
, and is cleared
4.5.2 PLL
4.8
Circuit. If
4.8
4.6