MC68HC908MR16CFU Freescale Semiconductor, MC68HC908MR16CFU Datasheet - Page 183

• Manufacturer Part Number: MC68HC908MR16CFU
• Description: IC MCU 8MHZ 16K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908MR16CFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 44
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

14.2.3 Clocks in Wait Mode
In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules.
Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
14.3 Reset and System Initialization
The MCU has these reset sources:
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in monitor mode) and assert the
internal reset signal (IRST). IRST causes all registers to be returned to their default values and all
modules to be returned to their reset states.
An internal reset clears the SIM counter (see
the resets sets a corresponding bit in the SIM reset status register (SRSR). See
Register.
14.3.1 External Pin Reset
Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register
(SRSR) is set as long as RST is held low for a minimum of 67 CGMXCLK cycles, assuming that neither
the POR nor the LVI was the source of the reset. See
timing.
Freescale Semiconductor
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Power-on reset module (POR)
External reset pin (RST)
Computer operating properly (COP) module
Low-voltage inhibit (LVI) module
Illegal opcode
Illegal address
OSC1
PLL
CGMVCLK
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
MONITOR MODE
CIRCUIT
SELECT
CLOCK
USER MODE
BCS
CGM
Figure 14-2. CGM Clock Signals
PTC2
÷ 2
14.4 SIM
A
B S*
Table 14-2
*When S = 1,
CGMOUT = B
Counter), but an external reset does not. Each of
CGMXCLK
CGMOUT
for details.
Figure 14-3
Reset and System Initialization
÷ 2
SIM COUNTER
14.7.2 SIM Reset Status
SIM
shows the relative
GENERATORS
BUS CLOCK
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