MC68HC908MR16CFU Freescale Semiconductor, MC68HC908MR16CFU Datasheet - Page 210

• Manufacturer Part Number: MC68HC908MR16CFU
• Description: IC MCU 8MHZ 16K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908MR16CFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 44
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Serial Peripheral Interface Module (SPI)
When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as
a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can
still prevent the state of the SS from creating a MODF error. See
When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to
prevent multiple masters from driving MOSI and SPSCK. (See
the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN bit
is low for an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data
direction register of the shared I/O port. With MODFEN high, it is an input-only pin to the SPI regardless
of the state of the data direction register of the shared I/O port.
The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and
reading the port data register. See
15.11.5 V
V
reduce the ground return path loop and minimize radio frequency (RF) emissions, connect the ground pin
of the slave to the V
15.12 I/O Registers
Three registers control and monitor SPI operation:
15.12.1 SPI Control Register
The SPI control register (SPCR):
210
SS
•
•
•
•
•
•
•
•
•
is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. To
SPI control register, SPCR
SPI status and control register, SPSCR
SPI data register, SPDR
Enables SPI module interrupt requests
Selects CPU interrupt requests or DMA service requests
Configures the SPI module as master or slave
Selects serial clock polarity and phase
Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
Enables the SPI module
SPE
1. X = don’t care
0
1
1
1
SS
(Clock Ground)
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a
high-impedance state. The slave SPI ignores all incoming SPSCK clocks,
even if it was already in the middle of a transmission.
SPMSTR
X
0
1
1
(1)
SS
pin of the master.
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
MODFEN
X
X
0
1
Table
Table 15-3. SPI Configuration
Master without MODF
SPI Configuration
Master with MODF
15-3.
Not enabled
Slave
NOTE
General-purpose I/O; SS ignored by SPI
General-purpose I/O; SS ignored by SPI
15.6.2 Mode Fault
15.12.2 SPI Status and Control
State of SS Logic
Input-only to SPI
Input-only to SPI
Error.) For the state of
Freescale Semiconductor
Register.