MC68HC908MR16CFU Freescale Semiconductor, MC68HC908MR16CFU Datasheet - Page 208

• Manufacturer Part Number: MC68HC908MR16CFU
• Description: IC MCU 8MHZ 16K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908MR16CFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 44
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Serial Peripheral Interface Module (SPI)
15.10 Low-Power Mode
The WAIT instruction puts the MCU in a low power-consumption standby mode.
The SPI module remains active after the execution of a WAIT instruction. In wait mode the SPI module
registers are not accessible by the CPU. Any enabled CPU interrupt request from the SPI module can
bring the MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power consumption by disabling the
SPI module before executing the WAIT instruction.
To exit wait mode when an overflow condition occurs, enable the OVRF bit to generate CPU interrupt
requests by setting the error interrupt enable bit (ERRIE). See
Since the SPTE bit cannot be cleared during a break with the BCFE bit cleared, a write to the transmit
data register in break mode does not initiate a transmission nor is this data transferred into the shift
register. Therefore, a write to the SPDR in break mode with the BCFE bit cleared has no effect.
15.11 I/O Signals
The SPI module has five I/O pins and shares four of them with a parallel I/O port. The pins are:
208
•
•
•
•
MISO — Data received
MOSI — Data transmitted
SPSCK — Serial clock
SS — Slave select
CPHA:CPOL = 1:0
WRITE TO SPDR
1
2
3
4 FIRST INCOMING BYTE TRANSFERS FROM SHIFT
5
6 CPU READS SPSCR WITH SPRF BIT SET.
READ SPSCR
CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT.
BYTE 1 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2
AND CLEARING SPTE BIT.
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
READ SPDR
SPSCK
SPTE
SPRF
MOSI
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
1
Figure 15-12. SPRF/SPTE CPU Interrupt Timing
MSBBIT
BYTE 1
2
6
BIT
5
3
BIT
4
BIT
3
BIT
2
BIT
1
10
11 CPU READS SPSCR WITH SPRF BIT SET.
12 CPU READS SPDR, CLEARING SPRF BIT.
7 CPU READS SPDR, CLEARING SPRF BIT.
8
9
LSBMSBBIT
5
4
CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE
3 AND CLEARING SPTE BIT.
SECOND INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
BYTE 3 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
BYTE 2
6
6
7
15.7
BIT
5
8
BIT
4
Interrupts.
BIT
3
BIT
2
BIT
1
LSBMSBBIT
10
9
BYTE 3
11
Freescale Semiconductor
6
12
BIT
5
BIT
4