MC68HC908MR16CFU Freescale Semiconductor, MC68HC908MR16CFU Datasheet - Page 251

• Manufacturer Part Number: MC68HC908MR16CFU
• Description: IC MCU 8MHZ 16K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908MR16CFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 44
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Chapter 18
Development Support
18.1 Introduction
This section describes the break module, the monitor read-only memory (MON), and the monitor mode
entry methods.
18.2 Break Module (BRK)
The break module (BRK) can generate a break interrupt that stops normal program flow at a defined
address to enter a background program. Features include:
18.2.1 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal to the CPU. The CPU then loads the instruction register with a software
interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors
to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
These events can cause a break interrupt to occur:
When a CPU-generated address matches the contents of the break address registers, the break interrupt
begins after the CPU completes its current instruction. A return-from-interrupt instruction (RTI) in the
break routine ends the break interrupt and returns the microcontroller unit (MCU) to normal operation.
Figure 18-1
18.2.1.1 Flag Protection During Break Interrupts
The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during
the break state.
Freescale Semiconductor
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Accessible input/output (I/O) registers during the break interrupt
Central processor unit (CPU) generated break interrupts
Software-generated break interrupts
Computer operating properly (COP) disabling during break interrupts
A CPU-generated address (the address in the program counter) matches the contents of the break
address registers.
Software writes a logic 1 to the BRKA bit in the break status and control register.
shows the structure of the break module.
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