MC68HC908MR16CFU Freescale Semiconductor, MC68HC908MR16CFU Datasheet - Page 147

• Manufacturer Part Number: MC68HC908MR16CFU
• Description: IC MCU 8MHZ 16K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908MR16CFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 44
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

LDOK— Load OK Bit
PWMEN — PWM Module Enable Bit
Freescale Semiconductor
This read/write bit loads the prescaler bits of the PMCTL2 register and the entire PMMODH/L and
PWMVALH/L registers into a set of buffers. The buffered prescaler divisor, PWM counter modulus
value, and PWM pulse will take effect at the next PWM load. Set LDOK by reading it when it is logic 0
and then writing a logic 1 to it. LDOK is automatically cleared after the new values are loaded or can
be manually cleared before a reload by writing a 0 to it. Reset clears LDOK.
This read/write bit enables and disables the PWM generator and the PWM pins. When PWMEN is
clear, the PWM generator is disabled and the PWM pins are in the high-impedance state (unless
OUTCTL = 1).
When the PWMEN bit is set, the PWM generator and PWM pins are activated.
For more information, see
1 = Load prescaler, modulus, and PWM values.
0 = Do not load new modulus, prescaler, and PWM values.
1 = PWM generator and PWM pins enabled
0 = PWM generator and PWM pins disabled
The ISENSx bits are not buffered. Changing the current sensing method
can affect the present PWM cycle.
The user should initialize the PWM registers and set the LDOK bit before
enabling the PWM.
A PWM CPU interrupt request can still be generated when LDOK is 0.
Current Correction Bits
1. The polarity of the ISx pin is latched when both the top and bottom PWMs are off. At
2. Current is sensed even with 0% and 100% duty cycle.
ISENS1 and ISENS0
the 0% and 100% duty cycle boundaries, there is no dead-time, so no new current
value is sensed.
00
01
10
11
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
12.7 Initialization and the PWMEN
Table 12-7. Correction Methods
Bits IPOL1, IPOL2, and IPOL3 are used for correction.
Current sensing on pins IS1, IS2, and IS3 occurs during the
dead-time.
Current sensing on pins IS1, IS2, and IS3 occurs at the half
cycle in center-aligned mode and at the end of the cycle in
edge-aligned mode.
NOTE
NOTE
Correction Method
Bit.
Control Logic Block
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