PPC8567EVTAUJJ Freescale Semiconductor, PPC8567EVTAUJJ Datasheet - Page 112

• Manufacturer Part Number: PPC8567EVTAUJJ
• Description: MCU PWRQUICC III 1023-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of PPC8567EVTAUJJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

PCI_AD[31:0]
PCI_C_BE[3:0]
PCI_GNT[4:1]
PCI_GNT0
PCI_IRDY
PCI_PAR
PCI_PERR
PCI_SERR
PCI_STOP
PCI_TRDY
30. This pin requires an external 4.7-kΩ pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively
33. PF[21:22] are multiplexed as cfg_dram_type[0:1]. THEY MUST BE VALID AT POWER-UP, EVEN BEFORE HRESET
35. When a PCI block is disabled, either the POR config pin that selects between internal and external arbiter must be pulled
36.MDIC[0] is grounded through an 18.2-Ω precision 1% resistor and MDIC[1] is connected to GV
39. If PCI is configured as PCI asynchronous mode, a valid clock must be provided on pin PCI_CLK . Otherwise the processor
41.These pins should be tied to SCOREGND through a 300 ohm resistor if the high speed interface is used.
43. It is highly recommended that unused SD_RX/SD_RX lanes should be powered down with lane_x_pd. Otherwise the
44. See
46. Must be high during HRESET. It is recommended to leave the pin open during HRESET since it has internal pullup resistor.
47. Must be pulled down with 4.7-kΩ resistor.
48. This pin must be left no connect.
49. A pull-up on LGPL4 is required for systems that boot from local bus (GPCM)-controlled NOR Flash.
Package and Pinout
Table 79
112
driven.
ASSERTION.
down to select external arbiter if there is any other PCI device connected on the PCI bus, or leave the PCIn_AD pins as "No
Connect" or terminated through 2–10 KΩ pull-up resistors with the default of internal arbiter if the PCIn_AD pins are not
connected to any other PCI device. The PCI block will drive the PCIn_AD pins if it is configured to be the PCI arbiter—through
POR config pins—irrespective of whether it is disabled via the DEVDISR register or not. It may cause contention if there is any
other PCI device connected on the bus.
1% resistor. These pins are used for automatic calibration of the DDR IOs.
will not boot up.
receivers will burn extra power and the internal circuitry may develop long term reliability problems.
Section 25.9, “Guidelines for High-Speed Interface
provides the pin-out listing for the MPC8567E 1023 FC-PBGA package.
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Signal
Signal
Table 78. MPC8568E Pinout Listing (continued)
AE19, AG20, AF19, AB20, AC20, AG21, AG22,
AB21, AF22, AH22, AE22, AF20, AB22, AE20,
AE23, AJ23, AJ24, AF27, AJ26, AE29, AH24,
AD24, AE25, AE26, AH27, AG27, AJ25, AE30,
AF26, AG26, AF28, AH26
AC22, AD20, AE28, AH25
AF29, AB18, AC18, AD18
AE18
AF23
AJ22
AF24
AD22
AE24
AK24
Table 79. MPC8567E Pinout Listing
Package Pin Number
Package Pin Number
Termination.”
PCI
Pin Type
Pin Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
DD
through an 18.2-Ω precision
Freescale Semiconductor
Supply
Power
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
Supply
Power
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
Notes
5,9,35
Notes
2,4
—
—
—
—
2
2
2
2