PPC8567EVTAUJJ Freescale Semiconductor, PPC8567EVTAUJJ Datasheet - Page 60

• Manufacturer Part Number: PPC8567EVTAUJJ
• Description: MCU PWRQUICC III 1023-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of PPC8567EVTAUJJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

PCI
Figure 30
Figure 37
60
HRESET high to first FRAME assertion
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
3. All PCI signals are measured from OV
4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
5. Input timings are measured at the pin.
6. The timing parameter t
7. The setup and hold time is with respect to the rising edge of HRESET.
8. The timing parameter t
9. The reset assertion timing requirement for HRESET is 100 μs.
10.Guaranteed by characterization
11.Guaranteed by design
block)(signal)(state) (reference)(state)
example, t
relative to the SYSCLK clock, t
PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the
valid (V) state.
for 3.3-V PCI signaling levels.
delivered through the component pin is less than or equal to the leakage current specification.
frequencies. The system clock period must be kept within the minimum and maximum defined ranges. For values
see
Bus Specifications.
Section 23,
provides the AC test load for PCI.
shows the PCI input AC timing conditions.
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
PCIVKH
“Clocking.”
Parameter
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V)
Table 49. PCI AC Timing Specifications at 66 MHz (continued)
Output
Figure 37. PCI Input AC Timing Measurement Conditions
PCRHFV
SYS
Input
CLK
indicates the minimum and maximum CLK cycle times for the various specified
SYS
for inputs and t
is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local
, reference (K) going to the high (H) state or setup time. Also, t
DD
Figure 36. PCI AC Test Load
/2 of the rising edge of PCI_CLK to 0.4 × OV
Z
0
t
PCIVKH
= 50 Ω
(first two letters of functional block)(reference)(state)(signal)(state)
Symbol
t
PCRHFV
1
R
Min
10
L
= 50 Ω
t
PCIXKH
(first two letters of functional
Max
OV
—
DD
DD
of the signal in question
/2
Freescale Semiconductor
PCRHFV
clocks
Unit
for outputs. For
symbolizes
Notes
8, 11