PPC8567EVTAUJJ Freescale Semiconductor, PPC8567EVTAUJJ Datasheet - Page 132

• Manufacturer Part Number: PPC8567EVTAUJJ
• Description: MCU PWRQUICC III 1023-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of PPC8567EVTAUJJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

System Design Information
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the V
smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating
to ensure the quick response time necessary. They should also be connected to the power and ground
planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS
tantalum or Sanyo OSCON).
25.4
The SerDes block requires a clean, tightly regulated source of power (SCOREVDD and XV
low jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is
outlined below.
Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections
from all capacitors to power and ground should be done with multiple vias to further reduce inductance.
25.5
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. All unused active low inputs should be tied to V
required. All unused active high inputs should be connected to GND. All NC (no-connect) signals must
remain unconnected. Power and ground connections must be made to all external V
BV
25.6
The MPC8568E requires weak pull-up resistors (2–10 kΩ is recommended) on open drain type pins
including I
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in
state under normal operating conditions as most have asynchronous behavior and spurious assertion will
give unpredictable results.
132
DD
•
•
•
, OV
First, the board should have at least 10 x 10-nF SMT ceramic chip capacitors as close as possible
to the supply balls of the device. Where the board has blind vias, these capacitors should be placed
directly below the chip supply and ground connections. Where the board does not have blind vias,
these capacitors should be placed in a ring around the device as close to the supply and ground
connections as possible.
Second, there should be a 1-µF ceramic chip capacitor on each side of the device. This should be
done for all SerDes supplies.
Third, between the device and any SerDes voltage regulator there should be a 10-µF, low
equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-µF, low ESR SMT
tantalum chip capacitor. This should be done for all SerDes supplies.
Connection Recommendations
SerDes Block Power Supply Decoupling Recommendations
Pull-Up and Pull-Down Resistor Requirements
2
DD
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
C pins and MPIC interrupt pins.
DD
, GV
Figure
, TV
DD
DD
and GND pins of the device.
75. Care must be taken to ensure that these pins are maintained at a valid deasserted
, BV
DD
, OV
DD
, GV
DD
, and LV
DD,
DD
TV
planes, to enable quick recharging of the
DD
, BV
DD
, OV
DD
, GV
DD,
Freescale Semiconductor
DD
L
and LV
VDD,
DD
) to ensure
TV
DD
DD
as
,