PPC8567EVTAUJJ Freescale Semiconductor, PPC8567EVTAUJJ Datasheet - Page 29

• Manufacturer Part Number: PPC8567EVTAUJJ
• Description: MCU PWRQUICC III 1023-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of PPC8567EVTAUJJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the
relevant eTSEC interface. That is, the transmit clock must be applied to the eTSECn’s TSECn_TX_CLK,
while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit
clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back out
onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is
intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a
source- synchronous timing reference. Typically, the clock edge that launched the data can be used, since
the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver. Note that there is
relationship between the maximum FIFO speed and the platform speed. For more information see Section
4.4, “Platform to FIFO restrictions.
A summary of the FIFO AC specifications appears in
Freescale Semiconductor
RX_CLK clock period
RX_CLK duty cycle
RX_CLK peak-to-peak jitter
Rise time RX_CLK (20%–80%)
Fall time RX_CLK (80%–20%)
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
TX_CLK, GTX_CLK clock period
TX_CLK, GTX_CLK duty cycle
TX_CLK, GTX_CLK peak-to-peak jitter
Rise time TX_CLK (20%–80%)
Fall time TX_CLK (80%–20%)
FIFO data TXD[7:0], TX_ER, TX_EN setup time to GTX_CLK
GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Parameter/Condition
Parameter/Condition
Table 25. FIFO Mode Transmit AC Timing Specification
Table 26. FIFO Mode Receive AC Timing Specification
t
Table 25
FIRH
Symbol
t
t
t
t
FIRDV
FIRDX
t
Symbol
t
FIRR
FIRF
FIRJ
FIR
t
t
t
t
t
FITDV
FITDX
/t
t
t
FITH
FITR
FITJ
FITF
FIT
FIRH
and
Min
5.0
1.5
0.5
45
Table
—
—
—
0.5
Min
5.0
2.0
45
—
—
—
1
26.
Ethernet Interface and MII Management
0.75
0.75
Typ
8.0
50
0.75
0.75
—
—
—
Typ
8.0
50
—
—
—
Max
100
250
Max
1.5
1.5
100
250
55
—
—
1.5
1.5
3.0
55
—
Unit
Unit
ns
ps
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
%
%
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