PPC8567EVTAUJJ Freescale Semiconductor, PPC8567EVTAUJJ Datasheet - Page 41

• Manufacturer Part Number: PPC8567EVTAUJJ
• Description: MCU PWRQUICC III 1023-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of PPC8567EVTAUJJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Figure 20
Figure 21
8.3
The electrical characteristics specified here apply to MII management interface signals MDIO
(management data input/output) and MDC (management data clock).
Freescale Semiconductor
At recommended operating conditions with L/TV
RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK
rising edge
Note:
1. The symbols used for timing specifications herein follow the pattern of t
(reference)(state)
t
relative to the t
receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the t
(K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based
on three letters representing the clock of a particular functional. For example, the subscript of t
MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise)
or F (fall).
MRDVKH
Ethernet Management Interface Electrical Characteristics
provides the AC test load for eTSEC.
shows the RMII receive AC timing diagram.
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V)
REF_CLK
RXD[1:0]
CRS_DV
RX_ER
Parameter/Condition
for inputs and t
MRX
clock reference (K) going to the high (H) state or setup time. Also, t
Table 36. RMII Receive AC Timing Specifications (continued)
Output
(first two letters of functional block)(reference)(state)(signal)(state)
Figure 21. RMII Receive AC Timing Diagram
t
RMRH
t
RMRDV
DD
Figure 20. eTSEC AC Test Load
of 3.3 V ± 5%.
t
RMR
Z
0
= 50 Ω
Valid Data
Symbol
t
RMRF
t
RMRDX
1
R
t
RMRDX
t
L
(first two letters of functional block)(signal)(state)
RMRR
= 50 Ω
Min
2.0
Ethernet Interface and MII Management
for outputs. For example,
LV
Typ
—
MRDXKL
DD
/2
MRX
MRX
symbolizes MII
Max
—
clock reference
represents the
Unit
ns
41