PPC8567EVTAUJJ Freescale Semiconductor, PPC8567EVTAUJJ Datasheet - Page 88

• Manufacturer Part Number: PPC8567EVTAUJJ
• Description: MCU PWRQUICC III 1023-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of PPC8567EVTAUJJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Serial RapidIO
Continuous Jitter Test Pattern (CJPAT) defined in Annex 48A of IEEE 802.3ae. All lanes of the LP-Serial
link shall be active in both the transmit and receive directions, and opposite ends of the links shall use
asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane
implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. The
amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10
The eye pattern shall be measured with AC coupling and the compliance template centered at 0 Volts
differential. The left and right edges of the template shall be aligned with the mean zero crossing points of
the measured data eye. The load for this test shall be 100 Ohms resistive +/– 5% differential to 2.5 GHz.
15.9.2
For the purpose of jitter measurement, the effects of a single-pole high pass filter with a 3 dB point at (Baud
Frequency)/1667 is applied to the jitter. The data pattern for jitter measurements is the Continuous Jitter
Test Pattern (CJPAT) pattern defined in Annex 48A of IEEE 802.3ae. All lanes of the LP-Serial link shall
be active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous
clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane implementations
shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. Jitter shall be measured
with AC coupling and at 0 Volts differential. Jitter measurement for the transmitter (or for calibration of a
jitter tolerance setup) shall be performed with a test procedure resulting in a BER curve such as that
described in Annex 48B of IEEE 802.3ae.
15.9.3
Transmit jitter is measured at the driver output when terminated into a load of 100 Ohms resistive +/– 5%
differential to 2.5 GHz.
15.9.4
Jitter tolerance is measured at the receiver using a jitter tolerance test signal. This signal is obtained by first
producing the sum of deterministic and random jitter defined in and then adjusting the signal amplitude
until the data eye contacts the 6 points of the minimum eye opening of the receive template shown in and
. Note that for this to occur, the test signal must have vertical waveform symmetry about the average value
and have horizontal symmetry (including jitter) about the mean zero crossing. Eye template measurement
requirements are as defined above. Random jitter is calibrated using a high pass filter with a low frequency
corner at 20 MHz and a 20 dB/decade roll-off below this. The required sinusoidal jitter specified in is then
added to the signal and the test load is replaced by the receiver being tested.
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MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Jitter Test Measurements
Transmit Jitter
Jitter Tolerance
Freescale Semiconductor
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