PPC8567EVTAUJJ Freescale Semiconductor, PPC8567EVTAUJJ Datasheet - Page 6

• Manufacturer Part Number: PPC8567EVTAUJJ
• Description: MCU PWRQUICC III 1023-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of PPC8567EVTAUJJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

MPC8568E Overview
1.2.6
The MPC8568E supports DDR SDRAM and DDR2 SDRAM. The memory interface controls main
memory accesses and provides for a maximum of 16 Gbytes of main memory.
The MPC8568E supports a variety of SDRAM configurations. SDRAM banks can be built using DIMMs
or directly-attached memory devices. Sixteen multiplexed address signals provide for device densities of
64 Mbits, 128 Mbits, 256 Mbits, 512 Mbits, 1 Gbits, 2 Gbits and 4 Gbits. Four chip select signals support
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TCP/IP acceleration and QoS features:
— IP v4 and IP v6 header recognition on receive
— IP v4 header checksum verification and generation
— TCP and UDP checksum verification and generation
— Per-packet configurable acceleration
— Recognition of VLAN, stacked (queue in queue) VLAN, 802.2, PPPoE session, MPLS stacks,
— Supported in all FIFO modes
— Transmission from up to eight physical queues
— Reception to up to eight physical queues
Full- and half-duplex Ethernet support (1000 Mbps supports only full duplex):
— IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or
IEEE Std 802.1™ virtual local area network (VLAN) tags and priority
VLAN insertion and deletion
Programmable Ethernet preamble insertion and extraction of up to 7 bytes
MAC address recognition
Ability to force allocation of header information and buffer descriptors into L2 cache
Ethernet standard interfaces
Ethernet reduced interfaces
FIFO and mixed interfaces
Both interfaces must use the same voltage (2.5 or 3.3 V).
and ESP/AH IP-security headers
software-programmed PAUSE frame generation and recognition)
– Per-frame VLAN control word or default VLAN for each eTSEC
– Extracted VLAN control word passed to software separately
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
DDR SDRAM Controller
Mode Option
Table 1. Supported eTSEC1 and eTSEC2 Configurations
TBI, GMII, MII, RTBI, RGMII, RMII,
RTBI, RGMII, or RMII
TBI, GMII, or MII
or 8-bit FIFO
16-bit FIFO
8-bit FIFO
eTSEC1
TBI, GMII, MII, RTBI, RGMII, RMII,
Not used/not available
RTBI, RGMII, or RMII
TBI, GMII, or MII
or 8-bit FIFO
8-bit FIFO
eTSEC2
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