PPC8567EVTAUJJ Freescale Semiconductor, PPC8567EVTAUJJ Datasheet - Page 48

• Manufacturer Part Number: PPC8567EVTAUJJ
• Description: MCU PWRQUICC III 1023-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of PPC8567EVTAUJJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus
48
Internal launch/capture clock to LCLK delay
Input setup to local bus clock (except LGTA/LUPWAIT)
LGTA/LUPWAIT input setup to local bus clock
Input hold from local bus clock (except LGTA/LUPWAIT)
LGTA/LUPWAIT input hold from local bus clock
LALE output transition to LAD/LDP output transition (LATCH hold time)
Local bus clock to output valid (except LAD/LDP and LALE)
Local bus clock to data valid for LAD/LDP
Local bus clock to address valid for LAD
Local bus clock to LALE assertion
Output hold from local bus clock (except LAD/LDP and LALE)
Output hold from local bus clock for LAD/LDP
Local bus clock to output high Impedance (except LAD/LDP and LALE)
Local bus clock to output high impedance for LAD/LDP
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
2. All timings are in reference to local bus clock for PLL bypass mode. Timings may be negative with respect to the local bus
3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
4. All signals are measured from BVDD/2 of the rising edge of local bus clock for PLL bypass mode to 0.4 x BVDD of the signal
5. Input timings are measured at the pin.
6. The value of t
7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through
8. Guaranteed by characterization.
9. Guaranteed by design.
for inputs and t
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock one(1). Also, t
output (O) going invalid (X) or output hold time.
clock because the actual launch and capture of signals is done with the internal launch/capture clock, which precedes LCLK
by t
complementary signals at BV
in question for 3.3-V signaling levels.
the component pin is less than or equal to the leakage current specification.
LBKHKT
.
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
LBOTOT
(First two letters of functional block)(reference)(state)(signal)(state)
LBKHOX
Table 43. Local Bus Timing Parameters—PLL Bypassed (continued)
is the measurement of the minimum time between the negation of LALE and any change in LAD
symbolizes local bus timing (LB) for the t
DD
Parameter
/2.
LBK
for outputs. For example, t
(First two letters of functional block)(signal)(state) (reference)(state)
LBK
clock reference (K) to go high (H), with respect to the
clock reference (K) goes high (H), in this case for
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
LBKLOV1
LBKLOV2
LBKLOV3
LBKLOV4
LBKLOX1
LBKLOX2
LBKLOZ1
LBKLOZ2
LBIVKH1
LBIXKH1
LBIVKL2
LBIXKL2
LBKHKT
LBOTOT
1
–1.8
–1.3
–3.7
–3.7
Min
2.3
6.2
6.1
1.5
—
—
—
—
—
—
LBIXKH1
Freescale Semiconductor
symbolizes local bus
Max
-0.3
-0.1
4.4
0.2
0.2
—
—
—
—
—
—
—
0
0
Unit Notes
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 5
4, 5
4, 5
4, 5
—
8
6
4
4
4
4
4
7
7