PPC8567EVTAUJJ Freescale Semiconductor, PPC8567EVTAUJJ Datasheet - Page 130

• Manufacturer Part Number: PPC8567EVTAUJJ
• Description: MCU PWRQUICC III 1023-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of PPC8567EVTAUJJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

System Design Information
25 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8568E.
25.1
This device includes six PLLs, as follows:
25.2
25.2.1
Each of the PLLs listed above is provided with power through independent power supply pins
(AV
level should always be equivalent to V
through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits per PLL power supply as illustrated in
AV
from one PLL to the other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
130
DD
1. The platform PLL generates the platform clock from the externally supplied SYSCLK input. The
2. The e500 core PLL generates the core clock using the platform clock as the input. The frequency
3. The PCI PLL generates the clocking for the PCI bus
4. The local bus PLL generates the clock for the local bus.
5. There is a PLL for the SerDes block.
6. QE PLL generates the QE clock from the externally supplied SYSCLK.
DD_PLAT
type pins. By providing independent filters to each PLL the opportunity to cause noise injection
Thermagon Inc.
4707 Detroit Ave.
Cleveland, OH 44102
Internet: www.thermagon.com
frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio
configuration bits as described in
ratio between the e500 core clock and the platform clock is selected using the e500 PLL ratio
configuration bits as described in
System Clocking
Power Supply Design and Sequencing
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
PLL Power Supply Filtering
, AV
DD_CORE
, AV
DD_PCI
, AV
DD
, and preferably these voltages will be derived directly from V
Section 23.2, “CCB/SYSCLK PLL Ratio.”
Section 23.3, “e500 Core PLL
DD_LBIU
, and AV
DD_SRDS
888-246-9050
, AV
Ratio.”
DD_CE
Figure
respectively). The AV
73, one to each of the
Freescale Semiconductor
DD
DD