PPC8567EVTAUJJ Freescale Semiconductor, PPC8567EVTAUJJ Datasheet - Page 55

• Manufacturer Part Number: PPC8567EVTAUJJ
• Description: MCU PWRQUICC III 1023-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of PPC8567EVTAUJJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

At recommended operating conditions (see
Figure 30
Figure 31
Figure 32
Freescale Semiconductor
JTAG external clock to output high impedance:
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of t
2. The symbols used for timing specifications herein follow the pattern of t
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to t
5. Non-JTAG signal output timing with respect to t
6. Guaranteed by design
The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
for inputs and t
device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
(K) going to the high (H) state or setup time. Also, t
signals (D) went invalid (X) relative to the t
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
provides the AC test load for TDO and the boundary-scan outputs.
provides the JTAG clock input timing diagram.
provides the TRST timing diagram.
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Table 45. JTAG AC Timing Specifications (Independent of SYSCLK)
External Clock
(first two letters of functional block)(reference)(state)(signal)(state)
TRST
Parameter
JTAG
Output
Figure 30. AC Test Load for the JTAG Interface
Figure 31. JTAG Clock Input Timing Diagram
Boundary-scan data
Table
VM
t
JTKHKL
Figure 32. TRST Timing Diagram
3).
JTG
VM
Z
VM = Midpoint Voltage (OV DD /2)
VM = Midpoint Voltage (OV DD /2)
0
clock reference (K) going to the high (H) state. Note that, in general, the clock
TCLK
t
= 50 Ω
JTG
TCLK
TDO
.
VM
JTDXKH
.
t
TRST
symbolizes JTAG timing (JT) with respect to the time data input
Symbol
t
t
JTKLOZ
JTKLDZ
VM
2
for outputs. For example, t
(first two letters of functional block)(signal)(state) (reference)(state)
R
VM
L
= 50 Ω
Min
TCLK
t
3
3
JTGR
to the midpoint of the signal in question.
OV
Max
DD
19
t
1
9
JTGF
/2
(continued)
JTDVKH
symbolizes JTAG
JTG
Unit
ns
Figure
clock reference
30).
Notes
5, 6
JTAG
55