PPC8567EVTAUJJ Freescale Semiconductor, PPC8567EVTAUJJ Datasheet - Page 9

• Manufacturer Part Number: PPC8567EVTAUJJ
• Description: MCU PWRQUICC III 1023-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of PPC8567EVTAUJJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

1.2.12
The MPC8568E PIC implements the logic and programming structures of the OpenPIC architecture,
providing for external interrupts (with fully nested interrupt delivery), message interrupts, internal-logic
driven interrupts, and global high-resolution timers. Up to 16 programmable interrupt priority levels are
supported.
The PIC can be bypassed to allow use of an external interrupt controller.
1.2.13
The MPC8568E provides an integrated four-channel DMA controller, which can transfer data between any
of its I/O or memory ports or between two devices or locations on the same port. The DMA controller also:
There are two I
devices for expansion and system development.
The DUART supports full-duplex operation and is compatible with the PC16450 and PC16550
programming models. 16-byte FIFOs are supported for both the transmitter and the receiver.
The MPC8568E local bus controller (LBC) port allows connections with a wide variety of external
memories, DSPs, and ASICs. Three separate state machines share the same external pins and can be
programmed separately to access different types of devices. The general-purpose chip select machine
(GPCM) controls accesses to asynchronous devices using a simple handshake protocol. The user
programmable machine (UPM) can be programmed to interface to synchronous devices or custom ASIC
interfaces. The SDRAM controller provides access to standard SDRAM. Each chip select can be configured
so that the associated chip interface can be controlled by the GPCM, UPM, or SDRAM controller. All may
exist in the same system. The local bus controller supports the following features:
1.2.14
In addition to low-voltage operation and dynamic power management, which automatically minimizes
power consumption of blocks when they are idle, four power consumption modes are supported: full on,
doze, nap, and sleep.
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Allows chaining (both extended and direct) through local memory-mapped chain descriptors.
Scattering, gathering, and misaligned transfers are supported. In addition, stride transfers and
complex transaction chaining are supported.
Local attributes such as snoop and L2 write stashing can be specified.
Multiplexed 32-bit address and data bus operating at up to 133 MHz
Eight chip selects support eight external slaves
Up to eight-beat burst transfers
32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
Three protocol engines available on a per-chip-select basis
Parity support
Default boot ROM chip select with configurable bus width (8, 16, or 32 bits)
Supports zero-bus-turnaround (ZBT) RAM
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Programmable Interrupt Controller (PIC)
DMA Controller, I
Power Management
2
C controllers. These synchronous, multimaster buses can be connected to additional
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C, DUART, and Local Bus Controller
MPC8568E Overview
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