PPC8567EVTAUJJ Freescale Semiconductor, PPC8567EVTAUJJ Datasheet - Page 71

• Manufacturer Part Number: PPC8567EVTAUJJ
• Description: MCU PWRQUICC III 1023-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of PPC8567EVTAUJJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

UI
V
V
T
T
MAX-JITTER
T
14.3
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)
of each other at all times. This is specified to allow bit rate clock sources with a +/– 300 ppm tolerance.
14.4
The following is a summary of the specifications for the physical layer of PCI Express on this device. For
further details as well as the specifications of the Transport and Data Link layer please use the PCI
EXPRESS Base Specification. REV. 1.0a document.
14.4.1
Table 51
specified at the component pins.
Freescale Semiconductor
TX-EYE
TX-EYE-MEDIAN-to-
TX-RISE
Notes:
1. Typical based on PCI Express Specification 2.0.
TX-DIFFp-p
TX-DE-RATIO
Symbol
t
REFPJ
Symbol
, T
TX-FALL
defines the specifications for the differential output at all transmitters (TXs). The parameters are
Phase jitter. Deviation in edge location with respect to mean
edge location
Clocking Dependencies
Physical Layer Specifications
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Differential Transmitter (TX) Output
Unit Interval
Differential
Peak-to-Peak
Output Voltage
De- Emphasized
Differential
Output Voltage
(Ratio)
Minimum TX Eye
Width
Maximum time
between the jitter
median and
maximum
deviation from
the median.
D+/D- TX Output
Rise/Fall Time
Parameter
Table 50. SD_REF_CLK and SD_REF_CLK AC Requirements
Table 51. Differential Transmitter (TX) Output Specifications
Parameter Description
399.88
0.125
–3.0
0.70
Min
0.8
—
Nom
–3.5
400
—
—
—
—
400.12
Max
–4.0
0.15
1.2
—
—
Units
dB
ps
UI
UI
UI
V
Each UI is 400 ps ± 300 ppm. UI does not account for
Spread Spectrum Clock dictated variations. See Note 1.
V
Ratio of the V
after a transition divided by the V
after a transition. See Note 2.
The maximum Transmitter jitter can be derived as
T
See Notes 2 and 3.
Jitter is defined as the measurement variation of the
crossing points (V
recovered TX UI. A recovered TX UI is calculated over
3500 consecutive unit intervals of sample data. Jitter is
measured using all edges of the 250 consecutive UI in
the center of the 3500 UI used for calculating the TX UI.
See Notes 2 and 3.
See Notes 2 and 5
TX-DIFFp-p
TX-MAX-JITTER
Min
–50
= 2*|V
TX-DIFFp-p
Typical
= 1 – T
—
TX-D+
TX-DIFFp-p
Comments
TX-EYE
– V
of the second and following bits
Max
TX-D-
50
= 0 V) in relation to a
= 0.3 UI.
| See Note 2.
TX-DIFFp-p
Units
ps
of the first bit
PCI Express
Notes
—
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