PPC8567EVTAUJJ Freescale Semiconductor, PPC8567EVTAUJJ Datasheet - Page 43

• Manufacturer Part Number: PPC8567EVTAUJJ
• Description: MCU PWRQUICC III 1023-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of PPC8567EVTAUJJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Figure 22
Freescale Semiconductor
MDC period
MDC clock pulse width high
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
MDC rise time
MDC fall time
Note:
1. The symbols used for timing specifications herein follow the pattern of t
(reference)(state)
t
outputs (D) are invalid (X) or data hold time. Also, t
to the time data input signals (D) reach the valid state (V) relative to the t
(H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F
(fall).
2. IEEE 802.3 standard specifies that the max MDC frequency to be 2.5MHz. The frequency is programmed through
3. This parameter is dependent on the platform clock speed. The delay is equal to 16 platform clock periods +/-3ns. With a
4. Guaranteed by design
5. t
6. MDC to MDIO data valid t
MDKHDX
MIIMCFG[MgmtClk].
platform clock of 333MHz, the min/max delay is 48ns +/- 3ns.
time – Max delay).
plb_clk
symbolizes management data timing (MD) for the time t
is the platform (CCB) clock period.
shows the MII management AC timing diagram.
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
for inputs and t
Parameters
Table 38. MII management AC timing specifications (continued)
MDKHDV
Figure 22. MII Management Interface Timing Diagram
(first two letters of functional block)(reference)(state)(signal)(state)
is a function of clock period and max delay time (t
t
t
t
Symbol
MDKHDX
MDDXKH
MDDVKH
t
t
t
t
MDCH
MDCR
MDCF
MDC
MDDVKH
(16*t
symbolizes management data timing (MD) with respect
Min
400
plb_clk
32
—
—
MDC
5
0
)-3
from clock reference (K) high (H) until data
MDC
(first two letters of functional block)(signal)(state)
(16*t
clock reference (K) going to the high
Max
plb_clk
10
10
—
—
—
—
for outputs. For example,
MDKHDX
Ethernet Interface and MII Management
)+3
). (Min Setup time = Cycle
Unit
ns
ns
ns
ns
ns
ns
ns
Notes
3, 5
—
—
—
2
4
4
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