PPC8567EVTAUJJ Freescale Semiconductor, PPC8567EVTAUJJ Datasheet - Page 63

• Manufacturer Part Number: PPC8567EVTAUJJ
• Description: MCU PWRQUICC III 1023-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of PPC8567EVTAUJJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

between 500 mV and –500 mV, in other words, V
phase. The peak differential voltage (V
is 1000 mV p-p.
13.2
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by
the corresponding SerDes lanes. The SerDes reference clocks inputs are SD_REF_CLK and
SD_REF_CLK.
The following sections describe the SerDes reference clock requirements and some application
information.
13.2.1
Figure 40
Freescale Semiconductor
•
•
•
•
The supply voltage requirements for SCOREVDD and XVDD are specified in
SerDes Reference Clock Receiver Reference Circuit Structure
— The SD_REF_CLK and SD_REF_CLK are internally AC-coupled differential inputs as shown
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. Refer to the
The maximum average current requirement that also determines the common mode voltage range
— When the SerDes reference clock differential inputs are DC coupled externally with the clock
— This current limitation sets the maximum common mode input voltage to be less than 0.4V
— If the device driving the SD_REF_CLK and SD_REF_CLK inputs cannot drive 50 ohms to
The input amplitude requirement
— This requirement is described in detail in the following sections.
SerDes Reference Clocks
shows a receiver reference diagram of the SerDes reference clocks.
in
termination to SCOREGND followed by on-chip AC-coupling.
Differential Mode and Single-ended Mode description below for further detailed requirements.
driver chip, the maximum average current allowed for each input pin is 8mA. In this case, the
exact common mode input voltage is not critical as long as it is within the range allowed by the
maximum average current of 8 mA (refer to the following bullet for more detail), since the
input is AC-coupled on-chip.
(0.4V/50 = 8mA) while the minimum common mode input level is 0.1V above SCOREGND.
For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output
driven by its current source from 0mA to 16mA (0-0.8V), such that each phase of the
differential input has a single-ended swing from 0V to 800mV with the common mode voltage
at 400mV.
SCOREGND DC, or it exceeds the maximum input current limitations, then it must be
AC-coupled off-chip.
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
SerDes Reference Clock Receiver Characteristics
Figure
40. Each differential clock input (SD_REF_CLK or SD_REF_CLK) has a 50-Ω
DIFFp
) is 500 mV. The peak-to-peak differential voltage (V
OD
is 500 mV in one phase and –500 mV in the other
High-Speed Serial Interfaces (HSSI)
Table 2
and
DIFFp-p
Table
63
3.
)