PPC8567EVTAUJJ Freescale Semiconductor, PPC8567EVTAUJJ Datasheet - Page 73

• Manufacturer Part Number: PPC8567EVTAUJJ
• Description: MCU PWRQUICC III 1023-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of PPC8567EVTAUJJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

RL
Z
Z
L
C
T
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in
3. A T
4. The Transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode
5. Measured between 20-80% at transmitter package pins into a test load as shown in
6. See Section 4.3.1.8 of the PCI Express Base Specifications Rev 1.0a
7. See Section 4.2.6.3 of the PCI Express Base Specifications Rev 1.0a
8. MPC8568E SerDes transmitter does not have C
14.4.2
The TX eye diagram in
Figure
There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in
time using the jitter median to locate the center of the eye diagram. The different eye diagrams will differ
in voltage depending whether it is a transition bit or a de-emphasized bit. The exact reduced voltage level
of the de-emphasized bit will always be relative to the transition bit.
The eye diagram must be valid for any 250 consecutive UIs.
Freescale Semiconductor
TX-SKEW
TX-DIFF-DC
TX-DC
crosslink
TX
any 250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in
Transmitter collected over any 250 consecutive TX UIs. The T
TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean.
The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed
to the averaged time value.
return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement
applies to all valid input levels. The reference impedance for return loss measurements is 50 Ω to ground for both the D+ and
D- line (that is, as measured by a Vector Network Analyzer with 50 ohm probes—see
C
TX-CM
TX
TX-EYE
Symbol
is optional for the return loss measurement.
51) in place of any real PCI Express interconnect + RX component.
= 0.70 UI provides for a total sum of deterministic and random jitter budget of T
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Transmitter Compliance Eye Diagrams
Table 51. Differential Transmitter (TX) Output Specifications (continued)
Common Mode
Return Loss
DC Differential
TX Impedance
Transmitter DC
Impedance
Lane-to-Lane
Output Skew
AC Coupling
Capacitor
Crosslink
Random
Timeout
Parameter
Figure 49
is specified using the passive compliance/test measurement load (see
Min
80
40
75
—
6
0
Nom
100
TX
—
—
—
—
—
built-in. An external AC Coupling capacitor is required.
500 +
Max
2 UI
120
200
—
—
1
TX-EYE-MEDIAN-to-MAX-JITTER
Units
ms
dB
ps
nF
Ω
Ω
Measured over 50 MHz to 1.25 GHz. See Note 4
TX DC Differential mode Low Impedance
Required TX D+ as well as D- DC Impedance during all
states
Static skew between any two Transmitter Lanes within a
single Link
All Transmitters shall be AC coupled. The AC coupling is
required either within the media or within the
transmitting component itself. See note 8.
This random timeout helps resolve conflicts in crosslink
configuration by eventually resulting in only one
Downstream and one Upstream Port. See Note 7.
Figure
Figure 51
TX-JITTER-MAX
median is less than half of the total
51). Note that the series capacitors
Comments
Figure
for both V
Figure 51
49)
= 0.30 UI for the
TX-D+
and measured over
and V
PCI Express
TX-D-
.
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