PPC8567EVTAUJJ Freescale Semiconductor, PPC8567EVTAUJJ Datasheet - Page 122

• Manufacturer Part Number: PPC8567EVTAUJJ
• Description: MCU PWRQUICC III 1023-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of PPC8567EVTAUJJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Clocking
23.2
The CCB clock is the clock that drives the e500 core complex bus (CCB) and is also called the platform
clock. The frequency of the CCB is set using the following reset signals, as shown in
Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also note
that the DDR data rate is the determining factor in selecting the CCB bus frequency, since the CCB
frequency must equal the DDR data rate.
For specifications on the PCI_CLK, refer to the PCI 2.2 Specification.
122
DDR/DDR2 Memory bus clock frequency
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the
2. The memory bus clock speed is half the DDR/DDR2 data rate, hence, half the platform clock frequency.
•
•
Local bus clock speed (for Local Bus Controller)
Notes:
1. The Local bus clock speed on LCLK[0:2] is determined by CCB clock divided by the Local Bus PLL ratio programmed
resulting SYSCLK frequency, e500 core frequency, and CCB clock frequency do not exceed their respective maximum
or minimum operating frequencies.
in LCCR[CLKDIV]. See the reference manual for more information on this.
SYSCLK input signal
Binary value on LA[28:31] at power up
LA[28:31] Signals
CCB/SYSCLK PLL Ratio
Binary Value of
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
0000
0001
0010
0011
0100
Characteristic
Characteristic
Table 81. DDR/DDR2 Memory Bus Clocking Specifications
CCB:SYSCLK Ratio
Table 82. Local Bus Clocking Specifications
Reserved
16:1
2:1
3:1
4:1
Table 83. CCB Clock Ratio
Maximum Processor Core Frequency
Maximum Processor Core Frequency
Min
166
800, 1000, 1333 MHz
Min
25
800, 1000, 1333 MHz
LA[28:31] Signals
Binary Value of
1000
1001
1010
1011
1100
Max
266
Max
166
CCB:SYSCLK Ratio
Reserved
MHz
Unit
10:1
12:1
MHz
Unit
8:1
9:1
Freescale Semiconductor
Table
83:
Notes
Notes
1, 2
1