PPC8567EVTAUJJ Freescale Semiconductor, PPC8567EVTAUJJ Datasheet - Page 121

• Manufacturer Part Number: PPC8567EVTAUJJ
• Description: MCU PWRQUICC III 1023-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of PPC8567EVTAUJJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

30. This pin requires an external 4.7-kΩ pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively
33. PF[21:22] are multiplexed as cfg_dram_type[0:1]. THEY MUST BE VALID AT POWER-UP, EVEN BEFORE HRESET
35. When a PCI block is disabled, either the POR config pin that selects between internal and external arbiter must be pulled down
36.MDIC[0] is grounded through an 18.2-Ω precision 1% resistor and MDIC[1] is connected to GV
39. If PCI is configured as PCI asynchronous mode, a valid clock must be provided on pin PCI_CLK . Otherwise the processor
41.These pins should be tied to SCOREGND through a 300 ohm resistor if the high speed interface is used.
43. It is highly recommended that unused SD_RX/SD_RX lanes should be powered down with lane_x_pd. Otherwise the receivers
44. See
46. Must be high during HRESET. It is recommended to leave the pin open during HRESET since it has internal pullup resistor.
47. Must be pulled down with 4.7-kΩ resistor.
48. This pin must be left no connect.
49. A pull-up on LGPL4 is required for systems that boot from local bus (GPCM)-controlled NOR Flash.
23 Clocking
This section describes the PLL configuration of the MPC8568E. Note that the platform clock is identical
to the core complex bus (CCB) clock.
23.1
Table 80
specifications for the DDR/DDR2 memory bus.
bus.
Freescale Semiconductor
e500 core processor frequency
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.
driven.
ASSERTION.
to select external arbiter if there is any other PCI device connected on the PCI bus, or leave the PCIn_AD pins as "No Connect"
or terminated through 2–10 KΩ pull-up resistors with the default of internal arbiter if the PCIn_AD pins are not connected to any
other PCI device. The PCI block will drive the PCIn_AD pins if it is configured to be the PCI arbiter—through POR config
pins—irrespective of whether it is disabled via the DEVDISR register or not. It may cause contention if there is any other PCI
device connected on the bus.
1% resistor. These pins are used for automatic calibration of the DDR IOs.
will not boot up.
will burn extra power and the internal circuitry may develop long term reliability problems.
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to
Section 25.9, “Guidelines for High-Speed Interface
Characteristic
provides the clocking specifications for the processor cores and
Clock Ranges
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Signal
Section 23.2, “CCB/SYSCLK PLL
Table 80. Processor Core Clocking Specifications
Table 79. MPC8567E Pinout Listing (continued)
Min
533
800 MHz
Max
Maximum Processor Core Frequency
800
Package Pin Number
Table 82
Min
533
Termination.”
Ratio,” and
1000 MHz
1000
provides the clocking specifications for the local
Max
Section 23.3, “e500 Core PLL
Min
533
1333 MHz
Table 81
Pin Type
1333
Max
DD
through an 18.2-Ω precision
provides the clocking
Ratio,” for ratio settings.
MHz
Unit
Supply
Power
Notes
1, 2
Clocking
Notes
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