PPC8567EVTAUJJ Freescale Semiconductor, PPC8567EVTAUJJ Datasheet - Page 46

• Manufacturer Part Number: PPC8567EVTAUJJ
• Description: MCU PWRQUICC III 1023-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of PPC8567EVTAUJJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus
Table 42
Figure 23
46
Local bus cycle time
Local bus duty cycle
LCLK[n] skew to LCLK[m] or LSYNC_OUT
Input setup to local bus clock (except
LGTA/UPWAIT)
LGTA/LUPWAIT input setup to local bus clock
Input hold from local bus clock (except
LGTA/LUPWAIT)
LGTA/LUPWAIT input hold from local bus clock
LALE output transition to LAD/LDP output
transition (LATCH hold time)
Local bus clock to output valid (except
LAD/LDP and LALE)
Local bus clock to data valid for LAD/LDP
Local bus clock to address valid for LAD
Local bus clock to LALE assertion
Output hold from local bus clock (except
LAD/LDP and LALE)
Output hold from local bus clock for LAD/LDP
Local bus clock to output high Impedance
(except LAD/LDP and LALE)
Local bus clock to output high impedance for
LAD/LDP
Note:
1. The symbols used for timing specifications herein follow the pattern of t
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BV
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through
6. t
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
8. Guaranteed by design.
for inputs and t
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock one(1). Also, t
output (O) going invalid (X) or output hold time.
bypass mode to 0.4 × BV
the component pin is less than or equal to the leakage current specification.
with the LBCR[AHD] parameter.
complementary signals at BV
LBOTOT
is a measurement of the minimum time between the negation of LALE and any change in LAD. t
describes the timing parameters of the local bus interface at BV
provides the AC test load for the local bus.
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
(First two letters of functional block)(reference)(state)(signal)(state)
Parameter
LBKHOX
Table 42. Local Bus Timing Parameters (BV
DD
symbolizes local bus timing (LB) for the t
of the signal in question for 3.3-V signaling levels.
DD
/2.
DD
/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL
Symbol
t
t
t
t
t
t
t
t
t
t
LBKH/
LBKSKEW
t
t
t
t
t
LBKHOV1
LBKHOV2
LBKHOV3
LBKHOV4
LBKHOX1
LBKHOX2
LBKHOZ1
LBKHOZ2
LBIVKH1
LBIVKH2
LBIXKH1
LBIXKH2
LBOTOT
t
LBK
t
LBK
1
LBK
Min
for outputs. For example, t
7.5
1.9
1.8
1.1
1.1
1.5
0.8
0.8
43
—
—
—
—
—
—
—
(First two letters of functional block)(signal)(state) (reference)(state)
LBK
clock reference (K) to go high (H), with respect to the
DD
clock reference (K) goes high (H), in this case for
= 2.5 V)—PLL Enabled
DD
= 2.5 V.
Max
150
3.0
3.2
3.2
3.2
2.6
2.6
12
57
—
—
—
—
—
—
—
LBIXKH1
Freescale Semiconductor
LBOTOT
symbolizes local bus
Unit
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
is programmed
Notes
7, 8
3, 4
3, 4
3, 4
3, 4
—
—
2
6
3
3
3
3
3
5
5