PPC8567EVTAUJJ Freescale Semiconductor, PPC8567EVTAUJJ Datasheet - Page 16

• Manufacturer Part Number: PPC8567EVTAUJJ
• Description: MCU PWRQUICC III 1023-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of PPC8567EVTAUJJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Input Clocks
At recommended operating conditions (see
4.2
Table 8
At recommended operating conditions (see
4.3
The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then
used as an input to the counters of the PIC and the Time Base unit of the e500. There is no need for jitter
specification. The minimum pulse width of the RTC signal should be greater than 2x the period of the CCB
clock. That is, minimum clock high time is 2 × t
no minimum RTC frequency. RTC may be grounded if not needed.
16
PCI_CLK frequency
PCI_CLK cycle time
PCI_CLK rise and fall time
PCI_CLK duty cycle
PCI_CLK jitter
Notes:
1. Rise and fall times for PCI_CLK are measured at 0.4 V and 2.7 V.
2. Timing is guaranteed by design and characterization.
3. This represents the total input jitter—short term and long term—and is guaranteed by design.
4. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow
cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.
SYSCLK jitter
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the
2. Rise and fall times for SYSCLK are measured at 0.4 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to
resulting SYSCLK frequency, e500 core frequency, and CCB clock frequency do not exceed their respective
maximum or minimum operating frequencies. Refer to
“e500 Core PLL
allow cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.
provides the PCI clock (PCI_CLK) AC timing specifications for the MPC8568E.
PCI Clock Timing
Real Time Clock Timing
Parameter/Condition
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Parameter/Condition
Ratio,” for ratio settings.
Table 7. SYSCLK AC Timing Specifications (continued)
Table 8. PCI_CLK AC Timing Specifications
Table
Table
t
KHK
3) with OV
3) with OV
Symbol
f
t
t
PCI_CLK
PCI_CLK
KH
/t
—
PCI_CLK
, t
Symbol
KL
—
CCB
DD
DD
Section 23.2, “CCB/SYSCLK PLL Ratio
, and minimum clock low time is 2 × t
= 3.3 V ± 165 mV
= 3.3 V ± 165 mV
Min
0.6
15
40
—
—
Min
—
Typical
Typical
.
.
1.0
—
—
—
—
—
+/– 150
+/– 150
Max
Max
66.7
2.3
60
—
Freescale Semiconductor
and
Unit
ps
MHz
Unit
Section 23.3,
ns
ns
ps
%
CCB
. There is
Notes
4, 5
Notes
3,4
—
—
1
2