W83627DHG-PT Nuvoton Technology Corporation of America, W83627DHG-PT Datasheet - Page 10

• Manufacturer Part Number: W83627DHG-PT
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG-PT

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

W83627DHG-P/W83627DHG-PT
List of Tables
Table 8-1 Temperature Data Format .............................................................................................. 36
Table 8-2 SST Command Summary ............................................................................................... 38
Table 8-3 Typical Temperature Values ........................................................................................... 39
Table 8-4 Fan Divisor Definition...................................................................................................... 44
Table 8-5 Divisor, RPM, and Count Relation .................................................................................. 44
TM
Table 8-6 Display Registers - at SMART FAN
I Mode ................................................................ 50
TM
Table 8-7 Relative Registers - at Thermal Cruise
Mode ............................................................. 51
TM
Table 8-8 Relative Registers-at Fan Speed Cruise
Mode ........................................................... 51
TM
Table 8-9 Display Register - in SMART FAN
III Mode ................................................................ 55
TM
Table 8-10 Relative Register - in SMART FAN
III Control Mode................................................. 55
TM
Table 8-11 Display Registers - in SMART FAN
III+ Mode........................................................... 57
Table 10-1 Base Address Setting ................................................................................................. 126
Table 10-2 SPI Address Map ........................................................................................................ 126
Table 10-3 MODE ......................................................................................................................... 127
Table 11-1 The Delays of the FIFO............................................................................................... 129
Table 11-2 FDC Registers............................................................................................................. 140
Table 12-1 Register Summary for UART ...................................................................................... 153
Table 13-1 Pin Descriptions for SPP, EPP, and ECP Modes ....................................................... 159
Table 13-2 EPP Register Addresses ............................................................................................ 160
Table 13-3 Address and Bit Map for SPP and EPP Modes .......................................................... 160
Table 13-4 ECP Mode Description................................................................................................ 163
Table 13-5 ECP Register Addresses ............................................................................................ 164
Table 13-6 Bit Map of the ECP Registers ..................................................................................... 164
Table 14-1 Bit Map of Status Register .......................................................................................... 172
Table 14-2 KBC Command Sets................................................................................................... 172
Table 15-1 Bit Map of Logical Device A, CR[E4h], Bits[6:5] ......................................................... 178
Table 15-2 Definitions of Mouse Wake-Up Events ....................................................................... 180
Table 15-3 Timing and Voltage Parameters of RSMRST# ........................................................... 181
Table 15-4 ..................................................................................................................................... 182
Table 15-5 Bit Map of Logical Device A, CR[E6h], Bits[3:1] ......................................................... 182
Table 15-6 ..................................................................................................................................... 183
Table 16-1 SERIRQ Sampling Periods ......................................................................................... 186
Publication Release Date: July 09, 2009
-IX-
Version 1.94