W83627DHG-PT Nuvoton Technology Corporation of America, W83627DHG-PT Datasheet - Page 166

• Manufacturer Part Number: W83627DHG-PT
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG-PT

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

12.2.5 UART FIFO Control Register (UFR) (Write only)
This register is used to control the FIFO functions of the UART.
12.2.6 Interrupt Status Register (ISR) (Read only)
This register reflects the UART interrupt status.
DEFAULT
DEFAULT
NAME
BIT
5-4
NAME
BIT
7-6
5-4
7
6
3
2
1
0
BIT
BIT
BIT 7
0
0
1
1
RX IAL (MSB). RX INTERRUPT ACTIVE
LEVEL.
RX IAL (LSB). RX INTERRUPT ACTIVE
LEVEL.
RESERVED.
DMA MODE SELECT. When this bit is set to logical 1, the DMA mode changes from
mode 0 to mode 1 if UFR bit 0 = 1.
TRANSMITTER FIFO RESET. Setting this bit to logical 1 resets the TX FIFO counter
logic to its initial state. This bit is automatically cleared afterwards.
RECEIVER FIFO RESET. Setting this bit to logical 1 resets the RX FIFO counter logic to
its initial state. This bit is automatically cleared afterwards.
FIFO ENABLE. This bit enables 16550 mode. This bit should be set to logical 1 before
the other UFR bits are programmed.
FIFOS ENABLED. These two bits are set to logical 1 when UFR, bit 0 = 1.
RESERVED. These two bits are always logical 0.
FIFOS ENABLED
RX IAL
(MSB)
7
0
7
0
BIT 6
0
1
0
1
RXIAL
(LSB)
6
0
6
0
5
0
RESERVED
NA
5
RESREVED
W83627DHG-P/W83627DHG-PT
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
4
0
NA
4
DESCRIPTION
DESCRIPTION
-156-
INTERRUPT
STATUS
SELECT
BIT2
MODE
DMA
3
0
These two bits are used to set the active
level of the receiver FIFO interrupt. The
active level is the number of bytes that
must be in the receiver FIFO to generate
an interrupt.
3
0
INTERRUPT
TRANSMITTER
Publication Release Date: July 09, 2009
STATUS
FIFO RESET
01
04
08
14
BIT1
2
0
2
0
INTERRUPT
STATUS
RECEIVER
BIT0
1
0
RESET
FIFO
1
0
INTERRUPT
Version 1.94
PENDING
ENABLE
0 IF
FIFO
0
1
0
0