W83627DHG-PT Nuvoton Technology Corporation of America, W83627DHG-PT Datasheet - Page 203

• Manufacturer Part Number: W83627DHG-PT
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG-PT

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

CR 24h. (Global Option; Default 0100_0ss0b)
Note1:
CR 25h. (Interface Tri-state Enable; Default 00h)
Disable Serial Peripheral Interface
Pin 2
Pin 19
Pin 58
Pin 118 BEEP
7~6
BIT
BIT
7
6
5
4
3
2
1
0
5
4
3
Reserved.
Reserved.
READ / WRITE
READ / WRITE
GP23
AUXFANIN1
Read Only
GP22
R / W
R / W
R / W
R / W
R / W
R / W
R / W
R / W
R / W
Select output type of CPUFANOUT1
=0 CPUFANOUT1 is Push-pull. (Default)
=1 CPUFANOUT1 is Open-drain.
CLKSEL => Input clock rate selection
= 0
= 1
Select output type of AUXFANOUT
=0 AUXFANOUT is Push-pull. (Default)
=1 AUXFANOUT is Open-drain.
Select output type of SYSFANOUT
=0 SYSFANOUT is Open-drain. (Default)
=1 SYSFANOUT is Push-pull.
Select output type of CPUFANOUT0
=0 CPUFANOUT0 is Open-drain. (Default)
=1 CPUFANOUT0 is Push-pull.
ENKBC => Enable keyboard controller
= 0
= 1
This bit is read-only, and it is set or reset by a power-on strapping pin (Pin
54, SOUTA).
ENROM => Enable Serial Peripheral Interface
= 0
= 1
This bit is set or reset by a power-on strapping pin (Pin 52, DTRA#).
Note 1
UARTBTRI
UARTATRI
PRTTRI
The clock input on pin 18 is 24 MHz.
The clock input on pin 18 is 48 MHz. (Default)
KBC is disabled after hardware reset.
KBC is enabled after hardware reset.
ROM is disabled after hardware reset.
ROM is enabled after hardware reset.
W83627DHG-P/W83627DHG-PT
-193-
Enable Serial Peripheral Interface
Pin 2
Pin 19
Pin 58
Pin 118 SO
DESCRIPTION
DESCRIPTION
s: value by strapping
SCK
SCE
SI
Publication Release Date: July 09, 2009
Version 1.94