W83627DHG-PT Nuvoton Technology Corporation of America, W83627DHG-PT Datasheet - Page 180

• Manufacturer Part Number: W83627DHG-PT
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG-PT

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

The W83627DHG-P hardware supports RLE decompression and can transfer compressed data to a
peripheral. Odd (RLE) compression is not supported in the hardware, however. In order to transfer
data in ECP mode, the compression count is written to ecpAFifo and the data byte is written to
ecpDFifo.
13.3.13 FIFO Operation
The FIFO threshold is set in LD0 CRO0, bit 6 ~ 3. All data transferred to or from the parallel port can
proceed in DMA or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO
is used in Parallel Port FIFO mode or ECP Parallel Port Mode. After a reset, the FIFO is disabled.
13.3.14 DMA Transfers
DMA transfers are always to or from the ecpDFifo, tFifo, or CFifo. DMA uses the standard PC DMA
services. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA
empties or fills the FIFO using the appropriate direction and mode. When the terminal count in the
DMA controller is reached, an interrupt is generated, and serviceIntr is asserted, which will disable the
DMA.
13.3.15 Programmed I/O (NON-DMA) Mode
The ECP and parallel port FIFOs can also be operated using interrupt-driven, programmed I/O.
Programmed I/O transfers are
The host must set dmaEn and serviceIntr to 0 and also must set the direction and state accordingly in
the programmed I/O transfers.
The ECP requests programmed I/O transfers from the host by activating the IRQ pin. The
programmed I/O empties or fills the FIFO using the appropriate direction and mode.
13.3.12.3. Data Compression
1. To the ecpDFifo at 400h and ecpAFifo at 000h
2. From the ecpDFifo located at 400h
3. To / from the tFifo at 400h.
W83627DHG-P/W83627DHG-PT
-170-
Publication Release Date: July 09, 2009
Version 1.94