W83627DHG-PT Nuvoton Technology Corporation of America, W83627DHG-PT Datasheet - Page 165

• Manufacturer Part Number: W83627DHG-PT
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG-PT

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

12.2.4 Handshake Status Register (HSR) (Read/Write)
This register reflects the current state of the four input pins used with handshake peripherals such as
modems and records changes on these pins.
DEFAULT
BIT
7-5
BIT
NAME
4
3
2
1
0
7
6
5
4
3
2
1
0
BIT
RESERVED.
INTERNAL LOOPBACK ENABLE. When this bit is set to logical 1, the UART enters
diagnostic mode, as follows:
(1) SOUT is forced to logical 1, and SIN is isolated from the communication link.
(2) The modem output pins are set to their inactive state.
(3) The modem input pins are isolated from the communication link and connect
Aside from the above connections, the UART operates normally. This method allows the
CPU to test the UART in a convenient way.
IRQ ENABLE. The UART interrupt output is enabled by setting this bit to logical 1. In
diagnostic mode, this bit is internally connected to the modem control input DCD#.
LOOPBACK RI INPUT. This bit is only used in the diagnostic mode. In diagnostic mode,
this bit is internally connected to the modem control input RI#.
RTS. Request to Send. This bit controls the RTS# output. The value of this bit is inverted
and output to RTS#.
DTR. Data Terminal Ready. This bit controls the DTR# output. The value of this bit is
inverted and output to DTR#.
DCD. Data Carrier Detect. This bit is the opposite of the DCD# input. This bit is
equivalent to bit 3 of HCR in the loopback mode.
RI. Ring Indicator. This bit is the opposite of the RI# input. This bit is equivalent to bit 2
of HCR in the loopback mode.
DSR. Data Set Ready. This bit is the opposite of the DSR# input. This bit is equivalent to
bit 0 of HCR in the loopback mode.
CTS. Clear to Send. This bit is the opposite of the CTS# input. This bit is equivalent to bit
1 of HCR in the loopback mode.
TDCD. DCD# Toggling. This bit indicates that the DCD# pin has changed state after
HSR was read by the CPU.
FERI. RI Falling Edge. This bit indicates that the RI# pin has changed from low to high
after HSR was read by the CPU.
TDSR. DSR# Toggling. This bit indicates that the DSR# pin has changed state after HSR
was read by the CPU.
TCTS. CTS# Toggling. This bit indicates that the CTS# pin has changed state after HSR
was read by the CPU.
internally as DTR(bit 0 of HCR) →DSR#, RTS (bit 1 of HCR) →CTS#, Loopback RI
input (bit 2 of HCR) → RI# and IRQ enable (bit 3 of HCR) →DCD#.
DCD
NA
7
NA
RI
6
DSR
NA
5
W83627DHG-P/W83627DHG-PT
DESCRIPTION
DESCRIPTION
-155-
CTS
NA
4
TDCD
NA
3
Publication Release Date: July 09, 2009
FERI
NA
2
TDSR
NA
1
Version 1.94
TCTS
NA
0