W83627DHG-PT Nuvoton Technology Corporation of America, W83627DHG-PT Datasheet - Page 7

• Manufacturer Part Number: W83627DHG-PT
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG-PT

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

13.
14.
15.
16.
13.1
13.2
13.3
14.1
14.2
14.3
14.4
14.5
15.1
15.2
15.3
15.4
16.1
16.2
PARALLEL PORT ................................................................................................................... 159
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.2.6
13.2.7
13.3.1
13.3.2
13.3.3
13.3.4
13.3.5
13.3.6
13.3.7
13.3.8
13.3.9
13.3.10
13.3.11
13.3.12
13.3.13
13.3.14
13.3.15
KEYBOARD CONTROLLER................................................................................................... 171
14.5.1
14.5.2
POWER MANAGEMENT EVENT........................................................................................... 176
15.1.1
15.1.2
15.2.1
15.2.2
15.4.1
SERIALIZED IRQ.................................................................................................................... 185
Printer Interface Logic....................................................................................................... 159
Enhanced Parallel Port (EPP)........................................................................................... 160
Extended Capabilities Parallel (ECP) Port........................................................................ 163
Output Buffer..................................................................................................................... 171
Input Buffer........................................................................................................................ 171
Status Register ................................................................................................................. 172
Commands........................................................................................................................ 172
Hardware GATEA20/Keyboard Reset Control Logic........................................................ 174
Power Control Logic.......................................................................................................... 177
Wake Up the System by Keyboard and Mouse ................................................................ 179
Resume Reset Logic......................................................................................................... 181
PWROK Generation.......................................................................................................... 181
Start Frame ....................................................................................................................... 185
IRQ/Data Frame................................................................................................................ 186
Data Port (Data Swapper) .......................................................................................................160
Printer Status Buffer ................................................................................................................161
Printer Control Latch and Printer Control Swapper..................................................................161
EPP Address Port....................................................................................................................162
EPP Data Port 0-3 ...................................................................................................................162
EPP Pin Descriptions ..............................................................................................................162
EPP Operation.........................................................................................................................162
ECP Register and Bit Map.......................................................................................................164
Data and ecpAFifo Port ...........................................................................................................165
Device Status Register (DSR) .................................................................................................165
Device Control Register (DCR)................................................................................................165
CFIFO (Parallel Port Data FIFO) Mode = 010 .........................................................................166
ECPDFIFO (ECP Data FIFO) Mode = 011 ..............................................................................166
TFIFO (Test FIFO Mode) Mode = 110.....................................................................................166
CNFGA (Configuration Register A) Mode = 111......................................................................166
CNFGB (Configuration Register B) Mode = 111......................................................................166
KB Control Register .................................................................................................................174
Port 92 Control Register ..........................................................................................................175
PSON# Logic...........................................................................................................................177
AC Power Failure Resume ......................................................................................................178
Waken up by Keyboard events................................................................................................179
Waken up by Mouse events ....................................................................................................180
The Relation among PWROK/PWROK2, ATXPGD and FTPRST#.........................................182
ECR (Extended Control Register) Mode = all .....................................................................167
ECP Pin Descriptions..........................................................................................................168
ECP Operation....................................................................................................................169
FIFO Operation...................................................................................................................170
DMA Transfers....................................................................................................................170
Programmed I/O (NON-DMA) Mode ...................................................................................170
W83627DHG-P/W83627DHG-PT
-VI-
Publication Release Date: July 09, 2009
Version 1.94