W83627DHG-PT Nuvoton Technology Corporation of America, W83627DHG-PT Datasheet - Page 18

• Manufacturer Part Number: W83627DHG-PT
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG-PT

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

5.1
5.2
LFRAME#
DRVDEN0
LRESET#
SYMBOL
LAD[3:0]
SYMBOL
SERIRQ
PCICLK
TRAK0#
INDEX#
LDRQ#
IOCLK
STEP#
PME#
MOA#
DSA#
DIR#
WD#
WE#
WP#
LPC Interface
FDC Interface
PIN
10
11
13
14
PIN
24-
18
86
21
22
23
27
29
30
1
3
4
6
8
9
OD
OD
OD
OD
OD
OD
OD
IN
IN
IN
I/O
cs
cs
cs
I/OD
24
24
24
24
24
24
24
OD
I/O
IN
O
IN
IN
IN
I/O
12p3
12tp3
tsp3
tsp3
tsp3
tp3
12p3
Drive Density Select bit 0.
This Schmitt-trigger input from the disk drive is active-low when the
head is positioned over the beginning of a track marked by an index
hole. This input pin needs to connect a pulled-up 1-KΩ resistor to 5V
for Floppy Drive compatibility.
Motor A On. When set to 0, this pin activates disk drive A. This is an
open-drain output.
Drive Select A. When set to 0, this pin activates disk drive A. This is an
open-drain output.
Direction of the head step motor. An open-drain output.
Logic 1 = outward motion
Logic 0 = inward motion
Step output pulses.
pulse to move the head to another track.
Write data. This logic-low open-drain writes pre-compensation serial
data to the selected FDD. An open-drain output.
Write enable. An open-drain output.
Track 0. This Schmitt-trigger input from the disk drive is active-low
when the head is positioned over the outermost track. This input pin
needs to connect a pulled-up 1-KΩ resistor to 5V for Floppy Drive
compatibility.
Write protected. This active-low Schmitt input from the disk drive
indicates that the diskette is write-protected. This input pin needs to
connect a pulled-up 1-KΩ resistor to 5V for Floppy Drive compatibility.
12tp3
System clock input, either 24MHz or 48MHz. The actual
frequency must be specified in the register. The default value is
48MHz.
Generated PME event.
PCI-clock 33-MHz input.
Encoded DMA Request signal.
Serialized IRQ input / output.
These signal lines communicate address, control, and data
information over the LPC bus between a host and a peripheral.
Indicates the start of a new cycle or the termination of a broken
cycle.
Reset signal. It can be connected to the PCIRST# signal on the
host.
W83627DHG-P/W83627DHG-PT
-8-
This active-low open-drain output produces a
DESCRIPTION
DESCRIPTION
Publication Release Date: July 09, 2009
Version 1.94