W83627DHG-PT Nuvoton Technology Corporation of America, W83627DHG-PT Datasheet - Page 178

• Manufacturer Part Number: W83627DHG-PT
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG-PT

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

13.3.11 ECP Pin Descriptions
NStrobe (HostClk)
PD<7:0>
nAck (PeriphClk)
Busy (PeriphAck)
PError (nAckReverse)
BIT
4
3
2
1
0
NAME
1 1 0: Test Mode. The FIFO may be written and read in this mode, but the data is not
1 1 1: Configuration Mode. The confgA and confgB registers are accessible at 0x400
nERRINTREN. Read/Write (Valid only in the ECP mode)
1: Disables the interrupt generated on the asserting edge of nFault.
0: Enables the interrupt generated on the falling edge of nFault. This prevents interrupts
from being lost in the time between the read and the write of the ECR.
DMAEN. Read/Write.
1: Enables DMA.
0: Disables DMA unconditionally.
SERVICE INTR. Read/Write.
1: Disables DMA and all of the service interrupts. Writing a logical 1 to this bit does not
cause an interrupt.
0: Enables one of the following cases of interrupts. When one of the serviced interrupts
occurs, this bit is set to logical 1 by the hardware. This bit must be reset to logical 0 to re-
enable the interrupts.
(a) dmaEn = 1: During DMA, this bit is set to logical 1 when terminal count is reached.
(b) dmaEn = 0, direction = 0: This bit is set to logical 1 whenever there are writeIntr
(c) dmaEn = 0, direction = 1: This bit is set to logical 1 whenver there are readIntr
FULL. Read only.
1: The FIFO is completely full. It cannot accept another byte.
0: The FIFO has at least one free byte.
EMPTY. Read only.
1: The FIFO is completely empty.
0: The FIFO contains at least one byte of data.
threshold or more bytes free in the FIFO.
threshold or more valid bytes to be read from the FIFO.
transmitted on the parallel port.
and 0x401 in this mode.
TYPE
I/O
O
I
I
I
This pin loads data or address into the slave on its asserting edge
during write operations. This signal handshakes with Busy.
These signals contain address, data or RLE data.
This signal indicates valid data driven by the peripheral when
asserted. This signal handshakes with nAutoFd in reverse.
This signal deasserts to indicate that the peripheral can accept
data. In the reverse direction, it indicates whether the data lines
contain ECP command information or data. Normal data are
transferred when Busy (PeriphAck) is high, and an 8-bit command
is transferred when it is low.
This signal is used to acknowledge a change in the direction of the
transfer (asserted = forward). The peripheral drives this signal low
to
nAckReverse to determine when it is permitted to drive the data
bus.
acknowledge
W83627DHG-P/W83627DHG-PT
DESCRIPTION
-168-
nReverseRequest.
DESCRIPTION
Publication Release Date: July 09, 2009
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