W83627DHG-PT Nuvoton Technology Corporation of America, W83627DHG-PT Datasheet - Page 9

• Manufacturer Part Number: W83627DHG-PT
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG-PT

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

List of Figures
Figure 3-1 W83627DHG-P Block Diagram ....................................................................................... 5
Figure 4-1 Pin Layout for W83627DHG-P......................................................................................... 6
Figure 7-1 Structure of the Configuration Register ......................................................................... 27
Figure 7-2 Devices of I/O Base Address......................................................................................... 28
Figure 7-3 Configuration Register ................................................................................................... 28
Figure 7-4 Chip (Global) Control Registers..................................................................................... 30
Figure 8-1 LPC Bus' Reads from / Writes to Internal Registers...................................................... 33
Figure 8-2 Serial Bus Write to Internal Address Register Followed by the Data Byte .................... 34
Figure 8-3 Serial Bus Read from Internal Address Register........................................................... 34
Figure 8-4 Analog Inputs and Application Circuit of the W83627DHG-P........................................ 35
Figure 8-5 Monitoring Temperature from Thermistor...................................................................... 37
Figure 8-6 Monitoring Temperature from Thermal Diode (Voltage Mode)...................................... 37
Figure 8-7 Monitoring Temperature from Thermal Diode (Current Mode)...................................... 38
Figure 8-8 PECI Temperature......................................................................................................... 41
Figure 8-9 Temperature and Fan Speed Relation after Tbase Offsets .......................................... 42
Figure 8-10 Block Diagram for PECI 1.0......................................................................................... 43
Figure 8-11 FANOUT and Corresponding Temperature Sensors in SMART FAN
Figure 8-12 Mechanism of Thermal Curise
Figure 8-13 Mechanism of Thermal Curise
Figure 8-14 Mechanism of Fan Speed Cruise
Figure 8-15 Setting of SMART FAN
Figure 8-16 SMART FAN
Figure 8-17 SMART FAN
Figure 8-18 SMART FAN
Figure 8-19 SMI Mode of Voltage and Fan Inputs .......................................................................... 58
Figure 8-20 SMI Mode of SYSTIN I ................................................................................................ 60
Figure 8-21 SMI Mode of SYSTIN II ............................................................................................... 61
Figure 8-22 SMI Mode of CPUTIN .................................................................................................. 62
Figure 8-23 OVT# Modes of Temperature Inputs ........................................................................... 63
Figure 8-24 Caseopen Mechanism ................................................................................................. 64
Figure 14-1 Keyboard and Mouse Interface.................................................................................. 171
Figure 15-1 Power Control Mechanism......................................................................................... 177
Figure 15-2 Power Sequence from S5 to S0, then Back to S5..................................................... 178
Figure 15-3 The previous state is “on” - 3VCC falls to 2.6V and SUSB# keeps at 2.0V .............. 179
Figure 15-4 The previous state is “off” - 3VCC falls to 2.6V and SUSB# keeps at 0.8V .............. 179
Figure 15-5 Mechanism of Resume Reset Logic.......................................................................... 181
Figure 15-6 .................................................................................................................................... 181
Figure 15-7 .................................................................................................................................... 183
Figure 15-8 .................................................................................................................................... 183
Figure 15-9 .................................................................................................................................... 184
TM
TM
TM
III Mechanism (Current Temp. > Target Temp. + Tol.) ...................... 53
III Mechanism (Current Temp. < Target Temp. - Tol.) ....................... 54
III+ Mechanism ................................................................................... 56
TM
III ........................................................................................ 53
W83627DHG-P/W83627DHG-PT
TM
TM
Mode (PWM Duty Cycle) ........................................ 49
Mode (DC Output Value) ........................................ 49
TM
-VIII-
Mode................................................................... 50
Publication Release Date: July 09, 2009
TM
I, III, and III+.47
Version 1.94