W83627DHG-PT Nuvoton Technology Corporation of America, W83627DHG-PT Datasheet - Page 159

• Manufacturer Part Number: W83627DHG-PT
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG-PT

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

In PS/2 mode, the bit definitions are as follows:
In PS/2 Model 30 mode, the bit definitions are as follows:
DEFAULT
DEFAULT
BIT
6-3
BIT
6-4
NAME
NAME
7
2
1
0
7
3
2
1
0
BIT
BIT
DSKCHG. This bit indicates the complement of the DSKCHG# input.
RESERVED. These bits are always logic 1 during a read.
DRATE1.
DRATE0.
HIGH DENS#.
0: 500 KB/S or 1 MB/S data rate (high-density FDD).
1: 250 KB/S or 300 KB/S data rate.
DSKCHG#. This bit indicates the status of the DSKCHG# input.
RESERVED. These bits are always a logic 0 during a read.
DMAEN. This bit indicates the value of DO register, bit 3.
NOPREC. This bit indicates the value of the NOPREC bit in the CC REGISTER.
DRATE1.
DRATE0.
DSKCHG#
DSKCHG
7
0
7
1
6
1
6
0
RESERVED
5
1
5
0
RESERVED
W83627DHG-P/W83627DHG-PT
DESCRIPTION
DESCRIPTION
-149-
4
1
4
0
These two bits select the data rate of the
FDC. See DR register bits 1 and 0 (Data
Rate Register (DR Register) (Write base
address + 4)) for how the settings
correspond to individual data rates.
These two bits select the data rate of the
FDC. See DR register bits 1 and 0 (Data
Rate Register (DR Register) (Write base
address + 4)) for how the settings
correspond to individual data rates.
DMAEN
3
1
3
0
Publication Release Date: July 09, 2009
NOPREC
DRATE1
2
1
2
0
DRATE0
DRATE1
1
0
1
1
Version 1.94
DRATE0
DENS#
HIGH
0
1
0
0