W83627DHG-PT Nuvoton Technology Corporation of America, W83627DHG-PT Datasheet - Page 72

• Manufacturer Part Number: W83627DHG-PT
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG-PT

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

(2) Comparator Interrupt Mode
8.7.2
The SMI#/OVT# pin is a multi-function pin. It can be in SMI# mode or in OVT# mode by setting
Configuration Register CR [29h], bit 6 to one or zero, respectively. In OVT# mode, it can monitor
temperatures, and it is enabled or disabled for SYSTIN, CPUTIN, and AUXTIN by Bank0 Index 18h,
bit 6; Bank0 Index 4Ch, bit 3; and Bank0 Index 4Ch, bit4.
The OVT# pin has two interrupt modes, comparator and interrupt. The modes are illustrated in this
figure.
T
(3) Two-Times Interrupt Mode
HYST
SMI#
T
This mode is enabled by setting Bank0 Index 4Ch, bit 6, to one.
In this mode, the SMI# pin can create an interrupt when the current temperature exceeds T
(Over Temperature) and continues to create interrupts until the temperature falls below T
This interrupt can be reset by reading all the interrupt status registers, or subsequent events do
not generate interrupts. This is illustrated in the figure below.
This mode is enabled by setting Bank0 Index 4Ch, bit 6, to zero.
In this mode, the SMI# pin can create an interrupt when the current temperature rises above T
or when the current temperature falls below T
however, and generates an interrupt, this mode does not generate additional interrupts, even if
the temperature remains above T
reset by reading all the interrupt status registers, or subsequent events do not generate interrupts.
This is illustrated in the figure above.
OI
OVT# Interrupt Mode
Comparator Interrupt Mode
*
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 8-22 SMI Mode of CPUTIN
*
O
, until the temperature falls below T
W83627DHG-P/W83627DHG-PT
*
-62-
T
HYST
HYST
SMI#
T
OI
. Once the temperature rises above T
Publication Release Date: July 09, 2009
Two-Time Interrupt Mode
*
HYST
. This interrupt must be
*
Version 1.94
HYST
*
O
O
O
.
,